AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 83

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.6.11
Datasheet
23:21
20:17
16:12
11:8
7:4
3:0
Bit
Access
C0CYCTRKRD - Channel 0 CYCTRK READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK RD Registers.
RW
RW
RW
RW
RW
RO
Default
00000b
Value
0000b
0000b
0000b
000b
0h
RST/PWR
Core
Core
Core
Core
Core
Core
Reserved
Reserved.
Min ACT To READ Delayed (C0sd_cr_act_rd):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank.
Corresponds to tRCD_rd at DDR Spec.
Same Rank Write To READ Delayed
(C0sd_cr_wrsr_rd):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the WRITE
and READ commands to the same rank.
Corresponds to tWTR at DDR Spec.
Different Ranks Write To READ Delayed
(C0sd_cr_wrdr_rd):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the WRITE
and READ commands to different ranks.
Corresponds to tWR_RD at DDR Spec.
Same Rank Read To Read Delayed
(C0sd_cr_rdsr_rd):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two READ
commands to the same rank.
Different Ranks Read To Read Delayed
(C0sd_cr_rddr_rd):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two READ
commands to different ranks.
Corresponds to tRD_RD.
0/0/0/MCHBAR
258-25Ah
000000h
24 bits
RO; RW;
Description
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