AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 85
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Processor Configuration Registers
Datasheet
26:24
19:17
15:14
13:10
9:1
Bit
23
22
21
20
16
0
Access
RW-L
RW-L
RW-L
RW-L
RW
RW
RW
RW
RW
RW
RO
000000000
Default
Value
0010b
000b
000b
00b
0b
0b
0b
0b
0b
0b
b
RST/PWR
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
CKE pulse width requirement in high phase
(sd0_cr_cke_pw_hl_safe):
This configuration register indicates CKE pulse width
requirement in high phase.
Corresponds to tCKE (high) at DDR Spec.
Rank 3 Population (sd0_cr_rankpop3):
1 - Rank 3 populated
0 - Rank 3 not populated
Rank 2 Population (sd0_cr_rankpop2):
1 - Rank 2 populated
0 - Rank 2 not populated
Rank 1 Population (sd0_cr_rankpop1):
1 - Rank 1 populated
0 - Rank 1 not populated
Rank 0 Population (sd0_cr_rankpop0):
1 - Rank 0 populated
0 - Rank 0 not populated
CKE pulse width requirement in low phase
(sd0_cr_cke_pw_lh_safe):
This configuration register indicates CKE pulse width
requirement in low phase.
Corresponds to tCKE (low) at DDR Spec.
Enable CKE toggle for PDN entry/exit
(sd0_cr_pdn_enable):
This configuration bit indicates that the toggling of CKE's
(for PDN entry/exit) is enabled.
Reserved
Reserved
Minimum Power-down exit to Non-Read command
spacing (sd0_cr_txp):
This configuration register indicates the minimum
number of clocks to wait following assertion of CKE
before issuing a non-read command.
1010-1111=Reserved.
0010-1001=2-9clocks.
0000-0001=Reserved.
Self refresh exit count (sd0_cr_slfrfsh_exit_cnt):
This configuration register indicates the Self refresh exit
count. (Program to 255).
Corresponds to tXSNR/tXSRD at DDR Spec.
Indicates only 1 DIMM populated
(sd0_cr_singledimmpop):
This configuration register indicates the that only 1 DIMM
is populated.
Description
85
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