AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 86

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.14
86
46:44
43:38
37:32
31:27
Bit
47
26
25
Access
C0REFRCTRL - Channel 0 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Settings to configure the DRAM refresh controller.
RW
RW
RW
RW
RW
RW
RO
010000b
011000b
Default
00110b
Value
010b
0b
0b
0b
RST/PWR
Core
Core
Core
Core
Core
Core
Core
Reserved
Reserved
Initial Refresh Count (sd0_cr_init_refrcnt):
Specifies the initial refresh count value.
Direct Rcomp Quiet Window (DIRQUIET):
This configuration setting indicates the amount of
refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
Indirect Rcomp Quiet Window (INDIRQUIET):
This configuration setting indicates the amount of
refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
Rcomp Wait (RCOMPWAIT):
This configuration setting indicates the amount of
refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
ZQCAL Enable (ZQCALEN):
This bit enables the DRAM controller to issue ZQCAL
command periodically.
Refresh Counter Enable (REFCNTEN):
This bit is used to enable the refresh counter to count
during times that DRAM is not in self-refresh, but
refreshes are not enabled. Such a condition may occur
due to need to reprogram DIMMs following DRAM
controller switch.
This bit has no effect when Refresh is enabled (i.e. there
is no mode where Refresh is enabled but the counter
does not run) So, in conjuction with bit 23 REFEN, the
modes are:
REFEN:REFCNTEN -- Description
0:0 -- Normal refresh disable
0:1 -- Refresh disabled, but counter is accumulating
refreshes.
1:X -- Normal refresh enable
0/0/0/MCHBAR
269-26Eh
241830000C30h
48 bits
RW; RO;
Processor Configuration Registers
Description
Datasheet
S