AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 88

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.15
88
31:12
13:0
11:8
7:4
3:0
Bit
Bit
Access
Access
RW
C0ODTCTRL - Channel 0 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
ODT controls
RW
RW
RW
RO
001100001
Default
Default
10000b
00000h
Value
Value
0000b
0000b
0000b
RST/PWR
RST/PWR
Core
Core
Core
Core
Core
Refresh Counter Time Out Value (REFTIMEOUT):
Program this field with a value that will provide 7.8 µs at
MCLK frequency.
At various MCLK frequencies this results in the following
values:
266 MHz -> 820 hex
333 MHz -> A28 hex
400 MHz -> C30 hex
533 MHz -> 104B hex
666 MHz -> 1450 hex
Reserved
DRAM ODT for Read Commands
(sd0_cr_odt_duration_rd):
Specifies the duration in MDCLKs to assert DRAM ODT for
Read Commands. The Async value should be used when
the Dynamic Power-down bit is set. Else use the Sync
value.
DRAM ODT for Write Commands
(sd0_cr_odt_duration_wr):
Specifies the duration in MDCLKs to assert DRAM ODT for
Write Commands. The Async value should be used when
the Dynamic Power-down bit is set. Else use the Sync
value.
IMC ODT for Read Commands
(sd0_cr_mchodt_duration):
Specifies the duration in MDCLKs to assert IMCODT for
Read Commands
0/0/0/MCHBAR
29C-29Fh
00000000h
32 bits
RW; RO;
Processor Configuration Registers
Description
Description
Datasheet