AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 89

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.6.16
Datasheet
31:24
23:16
15:8
7:0
Bit
Access
RW-L
RW-L
RW-L
RW-L
C0GTEW - Channel 0 Memory Controller Throttling Event
Weights.
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Programmable Event weights that are input into the averaging filter. Each Event weight
is an normalized 8 bit value that the BIOS must program. The BIOS must account for
burst length, 1N/2N rule considerations. It is also possible for BIOS to take into account
type loading variations of memory caused as a function of memory types and
population of ranks. All bits in this register can be locked by the GTLOCK bit in the
C0GTC register.
Default
Value
00h
00h
00h
00h
RST/PWR
Core
Core
Core
Core
Read Weight (RDW):
This value is input to the filter if in a given clock there is a
valid read command being issued on the memory bus.
Write Weight (WRTW):
This value is input to the filter if in a given clock there is a
valid write command being issued on the memory bus.
Command Weight (COMW):
This value is input to the filter if in a given clock there is a
valid command other than a read or write being issued on
the memory bus. BIOS Requirement: When operating
with 2N command rates, the scale for this field is twice
that of the read, write, or idle commands. For example, if
a read command had a weight of 02h, to program a
precharge of the same weight, the value 01h would be
entered in this field. BIOS must never allow a value
greater than 7Fh in this field when in 2N operation.
Idle Weight (IDLEW):
This value is input to the filter if in a given clock there is
no command being issued on the memory bus. If
command and address are tri-stated a value of “0” is
input to the filter
0/0/0/MCHBAR
2A0-2A3h
00000000h
32 bits
RW-L;
Description
89