AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet
AU80610004671AAS LBMH
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... Intel® Atom and D500 Series Datasheet – Volume This is volume Refer to document 322844 for Volume 1 June 2010 TM Processor D400 Document Number : 322845-002 ...
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... Current characterized errata are available on request. Code Names are for use by Intel to identify products, platforms, programs, services, etc. in development by Intel that have not been made commercially available to the public, i.e., launched or shipped. They are never to be used as "commercial" names for products or intended to function as trademarks ...
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Contents 1 Processor Configuration Registers ........................................................................ 8 1.1 Register Terminology .............................................................................. 8 1.2 System Address Map ............................................................................ 10 1.2.1 Legacy Address Range ............................................................. 12 1.2.2 Main Memory Address Range ( TOLUD) ............................. 15 ...
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BGSM - Base of GTT stolen Memory ........................................... 58 1.5.34 TSEGMB - TSEG Memory Base ................................................... 59 1.5.35 TOLUD - Top of Low Usable DRAM ............................................. 59 1.5.36 ERRSTS - Error Status ............................................................. 61 1.5.37 ...
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DID - Device Identification ...................................................... 105 1.9.3 PCICMD2 - PCI Command ....................................................... 106 1.9.4 PCISTS2 - PCI Status ............................................................. 107 1.9.5 RID2 - Revision Identification .................................................. 108 1.9 Class Code .................................................................... 109 ...
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MAXLAT - Maximum Latency ................................................... 141 1.10.17 CAPID0 - Mirror of Device 0 Capability Identifier ........................ 142 1.10.18 MGGC - Mirror of Dev 0 GMCH Graphics Control Register ............ 143 1.10.19 DEVEN - Device Enable .......................................................... ...
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Revision History Revision Number 001 • Initial Release 002 • No update. Matched with the revision number of volume 1 Datasheet Description § Revision Date December 2009 June 2010 7 ...
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... Processor Configuration Registers This is Volume 2 of the Intel® Atom and is intended to be distributed as part of the complete document. This document provides register information for the processor. 1.1 Register Terminology The following table shows the register-related terminology that is used in this document. Item RO Read Only bit(s) ...
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Processor Configuration Registers Item RW1C-S Read/Write 1 to Clear/Sticky bit(s). These bits can be read. Internal events may set this bit. A software write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no ...
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Item W Write-only. These bits may be written by software, but will always return zeros when read. They are used for write side-effects. Any data written to these registers cannot be retrieved. W1C Write 1 to Clear-only. These bits may ...
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Processor Configuration Registers PCIEXBAR – Flat memory-mapped address spaced to access device configuration registers. This mechanism can be used to access PCI configuration space (0-FFh) and Extended configuration space (100h-FFFh) for PCI Express devices. This enhanced configuration access mechanism is ...
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Figure 1-1. System Address Ranges 1.2.1 Legacy Address Range This area is divided into the following address regions: • 640 KB – DOS Area • 640 - 768 KB – Legacy Video Buffer Area • 768 - 896 ...
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Processor Configuration Registers Figure 1-2. DOS Legacy Address Range 1.2.1.1 DOS Range (0h – 9_FFFFh) The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main memory controlled by the processor. 1.2.1.2 Legacy ...
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Compatible SMRAM Address Range (A_0000h-B_FFFFh) When compatible SMM space is enabled, SMM-mode CPU accesses to this range are routed to physical system DRAM at 000A 0000h - 000B FFFFh. Non-SMM-mode CPU accesses to this range are considered ...
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Processor Configuration Registers Non-snooped accesses from DMI to this region are always sent to DRAM. Table 1-2. Extended System BIOS Area Memory Segments Memory Segments 0E0000H – 0E3FFFH 0E4000H – 0E7FFFH 0E8000H – 0EBFFFH 0EC000H – 0EFFFFH 1.2.1.5 System BIOS ...
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IMC to the DRAM unless it falls into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory. Figure 1-3. Main Memory Address Range 1.2.2.1 ISA Hole ...
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Processor Configuration Registers 1.2.2.2 TSEG TSEG is optionally 1 MB size. TSEG is below IGGTT stolen memory, which is at the top of Low Usable physical memory (TOLUD). SMM-mode CPU accesses to enabled TSEG ...
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PCI* Memory Address Range (TOLUD - 4 GB) This address range, from the top of low usable DRAM (TOLUD normally mapped to the DMI Interface. Device 0 exceptions are: Addresses decoded to the egress port ...
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Processor Configuration Registers Figure 1-4. PCI Memory Address Range 1.2.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh) This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the PCH portion of the chipset, but may also exist as stand-alone ...
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Processor accesses to the default IOAPIC region (FEC0_0000h to FECF_FFFFh) are always forwarded to DMI. 1.2.3.2 HSEG (FEDA_0000h-FEDB_FFFFh) This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to SMM Memory sometimes called the High SMM ...
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Processor Configuration Registers TOLUD register is restricted memory (A[31:20]), but processor can support up to 8GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD register helps identify the address range in between ...
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Graphics Memory Address Ranges The processor can be programmed to direct memory accesses to IGD when addresses are within any of five ranges specified via registers in processor’s Device #2 configuration space. Note: The Memory Map Base Register (MMADR) ...
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Processor Configuration Registers Compatible Transaction Address (Adr C) High Transaction Address (Adr H) TSEG Transaction Address (Adr T) These abbreviations are used later in the table describing SMM Space Transaction Handling. SMM Space Enabled Compatible (C) High (H) TSEG (T) ...
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Global Enable G_SMRAME 1 1.2.7.4 SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode. BIOS software can use this ...
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Processor Configuration Registers translated address hits enabled SMM DRAM space, an error is recorded in the PGTBL_ER register. DMI Interface originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation GTT ...
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A set of I/O accesses (other than ones used for configuration space access) are consumed by the internal graphics device enabled. The mechanisms for internal graphics IO decode and the associated control is explained later. The I/O ...
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... When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Writes to “Reserved” registers have no effect on the CPU. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “ ...
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... PCI Device 0 The CPU/DMI controller registers are in Device 0 (D0), Function 0 (F0). Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to Reserved registers may return non-zero values. Writes to reserved locations may cause system failures. All registers that are defined in the latest PCI Local Bus Specification, but are not necessary or implemented in this component are simply not included in this document ...
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Processor Configuration Registers Register Register Name Symbol Register Device Enable DEVEN PCI Express PCIEXBAR Register Range Base Address Root Complex DMIBAR Register Range Base Address Programmable PAM0 Attribute Map 0 Programmable PAM1 Attribute Map 1 Programmable PAM2 Attribute Map 2 ...
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... 0/0/0/PCI 0-1h 8086h RO; 16 bits Default RST/P Value WR 8086h Core Vendor Identification Number (VID): PCI standard identification for Intel. Default Access Value 0000h RW/L; 00000000h RO; RW/L; 00000000h RO; RW/L; 00000000h RW/L; RO; 0010h RW/L; RO; 0000h RO; RWC/S; 0000h RO; RW; 0000h RO; RW; 00000000h RW; 000000000108 RO; ...
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... Device Identification Number (DID): Identifier assigned to the CPU Uncore core/primary PCI device. The device IDs for PNV family are: A000h Core A00X: Intel® Atom D500 Series for DT A01X: Intel® Atom Series for MB 0/0/0/PCI 4-5h 0006h RO; RW; 16 bits Default RST/ ...
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Bit Access Processor Configuration Registers Default RST/ Value PWR registers. The error status is reported in the ERRSTS, PCISTS, and DMIUEST registers. 0: The SERR ...
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Processor Configuration Registers Bit Access 0 RO 1.5.4 PCISTS - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: This status register reports the occurrence of error events on Device 0's PCI interface. Since the CPU Uncore Device 0 does ...
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Bit Access 10 RWC 2 Processor Configuration Registers Default RST/ Value PWR DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions ...
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Processor Configuration Registers 1.5.5 RID - Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the revision number of the CPU Uncore Device #0. These bits are read only and writes to this register have no effect. ...
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MLT - Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: Device #0 in the CPU Uncore is not a PCI master. Therefore this register is not implemented. Bit Access 7:0 RO 1.5.8 HDR - Header Type B/D/F/Type: ...
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Processor Configuration Registers 1.5.10 SID - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This value is used to identify a particular subsystem. Bit Access 15:0 RWO 1.5.11 CAPPTR - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: ...
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Bit Access 63:36 RO 35:12 RW/L 11 RW/L 1.5.13 MCHBAR - GMCH Memory Mapped Register Range Base B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the CPU Uncore Memory Mapped Configuration space. There ...
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Processor Configuration Registers Bit Access 13 RW/L 1.5.14 GGC - GMCH Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:10 RO 9:8 RW/L 7:4 RW/L Datasheet Default RST/ Value PWR 0000h Core Reserved (): ...
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Bit Access 3 RW Processor Configuration Registers Default RST/ Value PWR NOTE: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. BIOS Requirement: BIOS must not ...
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Processor Configuration Registers 1.5.15 DEVEN - Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: Allows for enabling/disabling of PCI devices and functions that are within the CPU Uncore. The table below the bit definitions describes the behavior of all ...
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PCIEXBAR - PCI Express Register Range Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the PCI Express configuration space. This window of addresses contains the 4KB of configuration space for each PCI ...
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Processor Configuration Registers Bit Access 27 RW/L 26 RW/L 25:3 RO 2:1 RW/L/K 0 RW/L Datasheet Default RST/ Value PWR 128MB Base Address Mask (128ADMSK): This bit is either part of the PCI Express Base 0b Core Address (R/W) or ...
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DMIBAR - Root Complex Register Range Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI ...
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Processor Configuration Registers RE - Read Enable. When the CPU read accesses to the corresponding memory segment are claimed by the CPU Uncore and directed to main memory. Conversely, when the host read accesses ...
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PAM1 - Programmable Attribute Map 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h- 0C7FFFh. Bit Access 7:6 RO 5:4 RW/L 3:2 RO 1:0 RW/L ...
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Processor Configuration Registers 1.5.20 PAM2 - Programmable Attribute Map 2 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h- 0CFFFFh. Bit Acces s 7:6 RO 5:4 RW/L ...
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PAM3 - Programmable Attribute Map 3 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h- 0D7FFFh. Bit Access 7:6 RO 5:4 RW/L 3:2 RO 1:0 RW/L ...
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Processor Configuration Registers 1.5.22 PAM4 - Programmable Attribute Map 4 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h- 0DFFFFh. Bit Acces s 7:6 RO 5:4 RW/L ...
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PAM5 - Programmable Attribute Map 5 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h- 0E7FFFh. Bit Access 7:6 RO 5:4 RW/L 3:2 RO 1:0 RW/L ...
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Processor Configuration Registers 1.5.24 PAM6 - Programmable Attribute Map 6 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h- 0EFFFFh. Bit Access 7:6 RO 5:4 RW/L 3:2 ...
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LAC - Legacy Access Control B/D/F/Type: Address Offset: Default Value: Access: Size: This 8-bit register controls a fixed DRAM hole from 15-16 MB. Bit Access 7 RW/L 6:0 RO 1.5.26 REMAPBASE - Remap Base Address Register B/D/F/Type: Address Offset: ...
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Processor Configuration Registers 1.5.27 REMAPLIMIT - Remap Limit Address Register B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:10 RO 9:0 RW/L 1.5.28 SMRAM - System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: The SMRAMC register ...
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Bit Access 4 RW/L/K 3 RW/L 2 Processor Configuration Registers Default RST/ Value PWR update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the ...
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Processor Configuration Registers 1.5.29 ESMRAMC - Extended System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory ...
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Bit Access 0 RW/L 1.5.30 TOM - Top of Memory B/D/F/Type: Address Offset: Default Value: Access: Size: This Register contains the size of physical memory. BIOS determines the memory size reported to the OS using this Register. Bit Access 15:10 ...
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Processor Configuration Registers 1.5.31 TOUUD - Top of Upper Usable Dram B/D/F/Type: Address Offset: Default Value: Access: Size: This 16 bit register defines the Top of Upper Usable DRAM. Configuration software must set this value to TOM minus all EP ...
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Bit Access 31:20 RW/L 19:0 RO 1.5.33 BGSM - Base of GTT stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT ...
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Processor Configuration Registers 1.5.34 TSEGMB - TSEG Memory Base B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory by subtracting the TSEG size (PCI Device ...
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BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This 20MB range at the very top of addressable memory space is lost to APIC. According to the above equation,TOLUD is originally calculated to: 4GB ...
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Processor Configuration Registers 1.5.36 ERRSTS - Error Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register is used to report various error conditions via the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to ...
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Bit Access 6 1.5.37 ERRCMD - Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the CPU Uncore responses to various system errors. Since the CPU Uncore does not have an SERRB ...
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Processor Configuration Registers Bit Access 1.5.38 SMICMD - SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register enables various errors to generate an SMI DMI special cycle. When an error ...
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... Core RESERVED () Capability Device ID (CDID): Identifier assigned to CPU primary PCI device. The device IDs for CPU family are: Identifier assigned to CPU primary PCI device. The device IDs for Intel® Atom family are: 000b Core A00X: Desktop A01X: Mobile The corresponding three bit capability ID ...
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Processor Configuration Registers Bit Access 37: 33:31 RO 30:28 RO 27:24 RO 23:16 ...
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Bit Access 7:0 RO 1.6 MCHBAR Register Register Name Symbol Channel Decode CHDECMISC Misc Channel 0 DRAM Rank Boundary C0DRB0 Address 0 Channel 0 DRAM Rank Boundary C0DRB1 Address 1 Channel 0 DRAM Rank Boundary C0DRB2 Address 2 Channel 0 ...
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Processor Configuration Registers Register Register Name Symbol Power Management PMSTS Status 1.6.1 CHDECMISC - Channel Decode Misc B/D/F/Type: Address Offset: Default Value: Access: Size: Misc. CHDEC/MAGEN configuration bits Bit Access 7 RW/L 6:5 RW/L 4 RW/L 1:0 RO ...
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C0DRB0 - Channel 0 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: Size: The DRAM Rank Boundary Registers define the upper boundary address of each DRAM rank with a granularity of 64MB. Each rank has its ...
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Processor Configuration Registers 1.6.3 C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 B/D/F/Type: Address Offset: Default Value: Access: Size: See C0DRB0 Bit Access 15:10 RO 9:0 RW/L 1.6.4 C0DRB2 - Channel 0 DRAM Rank Boundary Address 2 B/D/F/Type: Address ...
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C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 B/D/F/Type: Address Offset: Default Value: Access: Size: See C0DRB0 Bit Access 15:10 RO 9:0 RW/L 1.6.6 C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute B/D/F/Type: Address Offset: Default Value: Access: ...
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Processor Configuration Registers DRA[6:0] = "00" means cfg0 , DRA[6:0] ="01" means cfg1 .... DRA[6:0] = "09" means cfg9 and so on. DRA[7] indicates whether it bank config or not. DRA[ means 4 bank, DRA[7] = ...
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C0DRA23 - Channel 0 DRAM Rank 2, 3 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: See C0DRA01 Bit Access 15:8 RW/L 7:0 RW/L 1.6.8 C0CYCTRKPCHG - Channel 0 CYCTRK PCHG B/D/F/Type: Address Offset: Default Value: Access: Size: Channel ...
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Processor Configuration Registers Bit Access 1:0 RW 1.6.9 C0CYCTRKACT - Channel 0 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Activate Registers. Bit Access 31:28 RO 27: 20:17 RW 16:13 RW Datasheet Default ...
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Bit Access 12:9 RW 8:0 RW 1.6.10 C0CYCTRKWR - Channel 0 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK WR Registers. Bit Acces s 15:12 RW 11:8 RW 7 Processor Configuration Registers ...
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Processor Configuration Registers 1.6.11 C0CYCTRKRD - Channel 0 CYCTRK READ B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK RD Registers. Bit Access 23:21 RO 20:17 RW 16:12 RW 11:8 RW 7:4 RW 3:0 RW Datasheet 0/0/0/MCHBAR 258-25Ah 000000h ...
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C0CYCTRKREFR - Channel 0 CYCTRK REFR B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Refresh Registers. Bit Access 15:13 RO 12:9 RW 8:0 RW 1.6.13 C0CKECTRL - Channel 0 CKE Control B/D/F/Type: Address Offset: Default Value: Access: ...
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Processor Configuration Registers Bit Access 23 RW/L 22 RW/L 21 RW/L 20 RW/L 19: 15:14 RO 13: Datasheet Default RST/ Value PWR Rank 3 Population (sd0_cr_rankpop3): 0b Core 1 - Rank 3 ...
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C0REFRCTRL - Channel 0 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: Access: Size: Settings to configure the DRAM refresh controller. Bit Access 47 RO 46:44 RW 43:38 RW 37:32 RW 31: ...
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Processor Configuration Registers Bit Access 21:20 RW 19:18 RW 17:16 RW 15:14 RW 13:0 RW Datasheet Default RST/ Value PWR This configuration bit enables (by default) that all the ranks are refreshed in a staggered/atomic fashion. ...
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C0ODTCTRL - Channel 0 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: ODT controls Bit Access 31:12 RO 11:8 RW 7 Processor Configuration Registers 0/0/0/MCHBAR 29C-29Fh 00000000h RO; RW; 32 bits Default RST/ Value ...
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Processor Configuration Registers 1.6.16 PMSTS - Power Management Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register is Reset by PWROK only. Bit Access 31 RWC/P 7 RWC/P Datasheet 0/0/0/MCHBAR F14-F17h 00000000h RWC/P; RO; 32 ...
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DMIBAR Register Name Register Symbol DMI Virtual DMIVCECH Channel Enhanced Capability DMI Port VC DMIPVCCAP1 Capability Register 1 DMI Port VC DMIPVCCAP2 Capability Register 2 DMI Port VC DMIPVCCTL Control DMI VC0 Resource DMIVC0RCAP Capability DMI VC0 Resource DMIVC0RCTL0 ...
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Processor Configuration Registers Register Name Register Symbol DMI Link Status DMILSTS 1.7.1 DMIVCECH - DMI Virtual Channel Enhanced Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates DMI Virtual Channel capabilities. Bit Access 31:20 RO 19:16 RO 15:0 RO Datasheet ...
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DMIPVCCAP1 - DMI Port VC Capability Register 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access 31 2:0 RWO 84 Processor ...
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Processor Configuration Registers 1.7.3 DMIPVCCAP2 - DMI Port VC Capability Register 2 B/D/F/Type: Address Offset: Default Value: Access: Size: Describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access 31:24 RO 23:8 RO 7:0 RO 1.7.4 ...
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DMIVC0RCAP - DMI VC0 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31: 22: 14:8 RO 7:0 RO 1.7.6 DMIVC0RCTL0 - DMI VC0 Resource Control B/D/F/Type: Address Offset: Default Value: ...
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Processor Configuration Registers Bit Access 23:20 RO 19:17 RW 16 1.7.7 DMIVC0RSTS - DMI VC0 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: Reports the Virtual Channel specific status. Bit Access 15 ...
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Bit Access 0 RO 1.7.8 DMIVC1RCAP - DMI VC1 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31: 22: 14 Processor Configuration Registers Default RST/ Value PWR ...
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Processor Configuration Registers 1.7.9 DMIVC1RCTL1 - DMI VC1 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: Controls the resources associated with PCI Express Virtual Channel 1. Bit Access 31 RW 30:27 RO 26:24 RW 23:20 RO 19:17 RW 16:8 ...
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Bit Access 7 1.7.10 DMIVC1RSTS - DMI VC1 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: Reports the Virtual Channel specific status. Bit Access 15 Processor Configuration Registers Default RST/ ...
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Processor Configuration Registers 1.7.11 DMIRCLDECH - DMI Root Complex Link Declaration B/D/F/Type: Address Offset: Default Value: Access: Size: This capability declares links from the respective element to other elements of the root complex component to which it belongs and to ...
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Bit Access 15:8 RO 7:4 RO 3:0 RO 1.7.13 DMILE1D - DMI Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: First part of a Link Entry which declares an internal link to another Root Complex Element. Bit ...
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Processor Configuration Registers Bit Access RWO 1.7.14 DMILE1A - DMI Link Entry 1 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry which declares an internal link to another Root Complex Element. ...
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DMILE2D - DMI Link Entry 2 Description B/D/F/Type: Address Offset: Default Value: Access: Size: First part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 31:24 RO 23:16 RWO 15 ...
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Processor Configuration Registers 1.7.16 DMILE2A - DMI Link Entry 2 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 63:36 RO 35:12 RWO ...
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DMILCAP - DMI Link Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates DMI specific capabilities. Bit Access 31:18 RO 17:15 RWO 14:12 RWO 11:10 RO 9 Processor Configuration Registers 0/0/0/DMIBAR 84-87h 00012C41h RO; RWO; ...
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Processor Configuration Registers Bit Access 1.7.19 DMILCTL - DMI Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: Allows control of DMI. Bit Acces 1:0 RW Datasheet Default RST/ Value PWR ...
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DMILSTS - DMI Link Status B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates DMI status. Bit Acces s 15:10 RO 9:4 RO 3:0 RO 1.8 EPBAR Register Name EP Element EPESD Self Description EP Link Entry 1 EPLE1D Description ...
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Processor Configuration Registers 1.8.1 EPESD - EP Element Self Description B/D/F/Type: Address Offset: Default Value: Access: Size: Provides information about the root complex element containing this Link Declaration Capability. Bit Access 31:24 RO 23:16 RWO 15:8 RO 7:4 RO 3:0 ...
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EPLE1D - EP Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: First part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 31:24 RO 23:16 RWO 15 ...
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Processor Configuration Registers 1.8.3 EPLE1A - EP Link Entry 1 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 63:36 RO 35:12 RWO ...
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Bit Access RWO 1.8.5 EPLE2A - EP Link Entry 2 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 63:28 ...
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Processor Configuration Registers Register Name Class Code CC Cache Line CLS Size Master Latency MLT2 Timer Header Type HDR2 Memory MMADR Mapped Range Address I/O Base IOBAR Address Graphics GMADR Memory Range Address Graphics GTTADR Translation Table Range Address Subsystem ...
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Register Name Software SSRW Scratch Read Write Base of Stolen BSM Memory Hardware HSRW Scratch Read Write Multi Size MSAC Aperture Control Secondary SCWBFC CWB Flush Control Capabilities CAPL List Control Message MSI_CAPID Signaled Interrupts Capability ID Message MC Control ...
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... Datasheet 0/2/0/PCI 0-1h 8086h RO; 16 bits Default RST/ Value PWR 8086h Core Vendor Identification Number (VID): PCI standard identification for Intel. 0/2/0/PCI 2-3h A001h RO; 16 bits Default RST/ Value PWR A001h Core Device Identification Number (DID): Device Identification Number (DID): This bit value Identifier assigned to the CPU Uncore core/primary PCI device ...
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PCICMD2 - PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses ...
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Processor Configuration Registers Bit Access 1.9.4 PCISTS2 - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant ...
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Bit Access 2:0 RO 1.9.5 RID2 - Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the revision number for Device #2 Functions 0 and ...
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Processor Configuration Registers 1.9 Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the IGD. This register also contains ...
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MLT2 - Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit Acces s 7:0 RO 1.9.9 HDR2 - Header ...
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Processor Configuration Registers Bit Access 31: 1.9.11 IOBAR - I/O Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register provides the Base offset of the I/O registers within Device ...
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GMADR - Graphics Memory Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: IGD graphics memory base address is specified in this register. Bit Access 31: RW/L 27 RW ...
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Processor Configuration Registers 1.9.13 GTTADR - Graphics Translation Table Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register requests allocation for Graphics Translation Table Range. The allocation is for 1 MB and the base address is defined by ...
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SID2 - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 RWO 1.9.16 ROMADR - Video BIOS ROM Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: The IGD does not use a separate BIOS ROM, ...
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Processor Configuration Registers 1.9.17 CAPPOINT - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:0 RO 1.9.18 INTRLINE - Interrupt Line B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:0 RW Datasheet 0/2/0/PCI 34h 90h RO; ...
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INTRPIN - Interrupt Pin B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:0 RO 1.9.20 MINGNT - Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Acces s 7:0 RO 1.9.21 MAXLAT - Maximum Latency B/D/F/Type: Address ...
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Processor Configuration Registers 1.9.22 CAPID0 - Mirror of Device 0 Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 63: 57:55 RO 54: ...
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Bit Access 37: 33:31 RO 30:28 RO 27:24 RO 23:16 RO 15:8 RO 7:0 RO 1.9.23 MGGC - GMCH Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:10 RO ...
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Processor Configuration Registers Bit Access 9:8 RO 7 Datasheet Default Description Value GTT Graphics Memory Size (GGMS): This field is used to select the amount of Main Memory that is pre-allocated to support ...
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DEVEN - Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: Allows for enabling/disabling of PCI devices and functions that are within the CPU Uncore. The table below the bit definitions describes the behavior of all combinations of transactions ...
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Processor Configuration Registers 1.9.25 SSRW - Software Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:0 RW 1.9.26 BSM - Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: Graphics Stolen Memory and Tseg ...
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HSRW - Hardware Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 RW 1.9.28 MSAC - Multi Size Aperture Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register determines the size of the graphics ...
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Processor Configuration Registers 1.9.29 SCWBFC - Secondary CWB Flush Control B/D/F/Type: Address Offset: Default Value: Access: Size: A CPU Dword/Qword write to this space flushes the Secondary CWB/DWB of all writes. The data is discarded. A CPU read to this ...
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MC - Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of ...
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Processor Configuration Registers Bit Access 0 RW 1.9. Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:2 RW 1:0 RO 1.9. Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 ...
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GDRST - Graphics Debug Reset B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7 126 Processor Configuration Registers 0/2/0/PCI C0h 00h RO; RW; 8 bits Default Description Value 0h Reserved (): ...
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Processor Configuration Registers 1.9.35 PMCAPID - Power Management Capabilities ID B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:8 RWO 7:0 RO 1.9.36 PMCAP - Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: This register is a ...
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Bit Access 2:0 RO 1.9.37 PMCS - Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15 RO 14: 7:2 RO 1:0 RW 128 Processor Configuration Registers Default ...
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Processor Configuration Registers Bit Access 1.9.38 SWSMI - Software SMI B/D/F/Type: Address Offset: Default Value: Access: Size: As long as there is the potential that DVO port legacy drivers exist which expect this register at this address, Dev#2F0 address E0h-E1h ...
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LBB - LBB-Legacy Backlight Brightness B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default This register can be accessed by either Byte, Word, or Dword PCI config cycles. A write to this register will cause the Backlight Event ...
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Processor Configuration Registers Register Name Memory MMADR Mapped Range Address Subsystem SVID2 Vendor Identification Subsystem SID2 Identification Video BIOS ROMADR ROM Base Address Capabilities CAPPOINT Pointer Minimum MINGNT Grant Maximum MAXLAT Latency Mirror of CAPID0 Device 0 Capability Identifier Mirror ...
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... Bit Access 15:0 RO 132 Processor Configuration Registers Register Register Register Symbol Start End 0/2/1/PCI 0-1h 8086h RO; 16 bits Default Description Value Vendor Identification Number (VID): 8086h PCI standard identification for Intel. Default Value Access 0001h RO; 0022h RO; 0000h RO; RW; 00000000h RO; 0000h RO; Datasheet ...
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Processor Configuration Registers 1.10.2 DID2 - Device Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This register is unique in Function 1 (the Function 0 DID is separate). This difference in Device ID is necessary for allowing distinct Plug and ...
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Bit Access 134 Processor Configuration Registers Default Description Value VGA Palette Snoop Enable (VGASNOOP): 0b This bit is hardwired disable snooping. Memory Write and Invalidate ...
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Processor Configuration Registers 1.10.4 PCISTS2 - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the ...
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Bit Access 3 RO 2:0 RO 1.10.5 RID2 - Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the revision number for Device #2 Functions 0 and 1 Bit Access 7:0 RO 136 Processor Configuration Registers Default ...
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Processor Configuration Registers 1.10 Class Code Register B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the IGD. This register also ...
Page 138
MLT2 - Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit Access 7:0 RO 1.10.9 HDR2 - Header Type ...
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Processor Configuration Registers 1.10.10 MMADR - Memory Mapped Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 KB and the base address is defined ...
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SID2 - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 RO 1.10.13 ROMADR - Video BIOS ROM Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: The IGD does not use a separate BIOS ROM, ...
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Processor Configuration Registers 1.10.14 CAPPOINT - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:0 RO 1.10.15 MINGNT - Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:0 RO 1.10.16 MAXLAT - Maximum Latency ...
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CAPID0 - Mirror of Device 0 Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 63: 57:55 RO 54: ...
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Processor Configuration Registers Bit Access 37: 33:31 RO 30:28 RO 27:24 RO 23:16 RO 15:8 RO 7:0 RO 1.10.18 MGGC - Mirror of Dev 0 GMCH Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: Bit ...
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Bit Access 7 144 Processor Configuration Registers Default Description Value Internal Graphics Translation Table. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled. 00: No memory pre-allocated. GTT cycles ...
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Processor Configuration Registers 1.10.19 DEVEN - Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: Allows for enabling/disabling of PCI devices and functions that are within the CPU Uncore. The table below the bit definitions describes the behavior of all ...
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SSRW - Mirror of Fun 0 Software Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:0 RO 1.10.21 BSM - Mirror of Func0 Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: Graphics ...
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Processor Configuration Registers 1.10.22 HSRW - Mirror of Dev2 Func0 Hardware Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 RO 1.10.23 MSAC - Mirror of Dev2 Func0 Multi Size Aperture Control B/D/F/Type: Address Offset: Default ...
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Bit Access 0:0 RO 1.10.24 GDRST - Mirror of Dev2 Func0 Graphics Debug Reset B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7 148 Processor Configuration Registers Default Description Value development requires ...
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Processor Configuration Registers 1.10.25 PMCAPID - Mirror of Fun 0 Power Management Capabilities ID B/D/F/Type: Address Offset: Default Value: Access: Size: This register is a mirror of function 0 with the same R/W attributes. The hardware implements a single physical ...
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Bit Access 2:0 RO 1.10.27 PMCS - Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15 RO 14: 7:2 RO 1:0 RW 150 Processor Configuration ...
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Processor Configuration Registers Bit Access 1.10.28 SWSMI - Mirror of Func0 Software SMI B/D/F/Type: Address Offset: Default Value: Access: Size: As long as there is the potential that DVO port legacy drivers exist which expect this register at this address, ...
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Device 2 IO Register Name MMIO Index Address Register MMIO Data Data Register 1.11.1 Index - MMIO Address Register B/D/F/Type: Address Offset: Default Value: Access: Size: MMIO_INDEX bit IO write to this port loads the offset of ...
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Processor Configuration Registers 1.11.2 Data - MMIO Data Register B/D/F/Type: Address Offset: Default Value: Access: Size: MMIO_DATA bit IO write to this port is re-directed to the MMIO register/GTT location pointed to by the MMIO-index register ...