AD5232BRUZ50 Analog Devices Inc, AD5232BRUZ50 Datasheet - Page 16

• Manufacturer Part Number: AD5232BRUZ50
• Description: IC,Digital Potentiometer,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5232BRUZ50

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 600 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5232-10EBZ - BOARD EVALUATION FOR AD5232-10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5232
Command bits are identified as Cx, address bits are Ax, and
data bits are Dx. The command instruction codes are defined
in Table 8. The SDO output shifts out the last eight bits of data
clocked into the serial register for daisy-chain operation, with
the following exception: after Command Instruction 9 or Com-
mand Instruction 10, the selected internal register data is present
in Data Byte 0. The command instructions following Command
Instruction 9 and Command Instruction 10 must be full 16-bit
Table 7. 16-Bit Serial Data Word
MSB
B15
C3
Table 8. Instruction/Operation Truth Table
Comm.
Inst.
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B15
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B14
C2
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B13
C1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Instruction Byte 1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B12
C0
A3
X
0
0
0
X
0
X
0
0
0
0
X
0
X
B11
A3
A2
X
0
0
0
X
0
X
0
0
0
0
X
0
X
ADDR
ADDR
A1
X
0
0
0
X
0
X
0
0
0
0
X
0
X
B10
A2
B8
A0
X
A0
A0
A0
X
A0
X
0
A0
A0
A0
X
A0
X
B9
A1
X
X
X
D7
X
X
X
X
X
X
X
X
X
X
X
B7
D7
D7
Rev. A | Page 16 of 24
X
X
X
X
X
X
X
X
X
X
X
X
D6
D6
X
X
D6
B8
A0
X
X
X
D5
X
X
X
X
X
X
X
X
X
X
D5
X
D5
data-words to completely clock out the contents of the serial
register. The RDACx register is a volatile scratch pad register
that is refreshed at power-on from the corresponding nonvol-
atile EEMEMx register. The increment, decrement, and shift
command instructions ignore the contents of Data Byte 0 in the
shift register. Execution of the operation noted in Table 8 occurs
when the CS strobe returns to logic high. Execution of an NOP
instruction minimizes power dissipation.
B7
D7
Data Byte 0
X
X
X
D4
X
X
X
X
X
X
X
D4
X
X
X
X
D4
B6
D6
X
X
X
D3
X
X
X
X
X
X
X
D3
X
X
X
X
D3
X
X
X
D2
X
X
X
X
X
X
X
D2
X
X
X
X
D2
B5
D5
D1
X
X
X
D1
X
X
X
X
X
X
X
D1
X
X
X
X
B4
D4
B0
D0
X
X
X
D0
X
X
X
X
X
X
X
D0
X
X
X
X
Operation
No operation (NOP). Do nothing.
Write contents of EEMEM (A0) to
the RDAC (A0) register. This com-
mand leaves the device in the read
program power state. To return
the part to the idle state, perform
Command Instruction 0 (NOP).
Save wiper setting. Write
contents of RDAC (ADDR) to
EEMEM (A0).
Write contents of Serial Register
Data Byte 0 to EEMEM (ADDR).
Decrement 6 dB right shift con-
tents of RDAC (A0). Stops at all 0s.
Decrement all 6 dB right shift
contents of all RDAC registers.
Stops at all 0s.
Decrement contents of RDAC (A0)
by 1. Stops at all 0s.
Decrement contents of all RDAC
registers by 1. Stops at all 0s.
Reset. Load all RDACs with their
corresponding, previously saved
EEMEM values.
Write contents of EEMEM(ADDR)
to Serial Register Data Byte 0.
Write contents of RDAC (A0) to
Serial Register Data Byte 0.
Write contents of Serial Register
Data Byte 0 to RDAC (A0).
Increment 6 dB left shift contents
of RDAC (A0). Stops at all 1s.
Increment all 6 dB left shift
contents of all RDAC registers.
Stops at all 1s.
Increment contents of RDAC (A0)
by 1. Stops at all 1s.
Increment contents of all RDAC
registers by 1. Stops at all 1s.
B3
D3
B2
D2
B1
D1
LSB
B0
D0