ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet

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ADSP-21161NKCAZ100

Manufacturer Part Number
ADSP-21161NKCAZ100
Description
IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21161NKCAZ100

Rohs Compliant
YES
Interface
Host Interface, Link Port, Serial Port
Clock Rate
100MHz
Non-volatile Memory
External
On-chip Ram
128kB
Voltage - I/o
3.30V
Voltage - Core
1.80V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
225-MBGA, 225-Mini-BGA
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
128KB
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (min)
1.71/3.13V
Operating Supply Voltage (max)
1.89/3.47V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
225
Package Type
CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP21161NKCAZ100

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SUMMARY
High performance 32-Bit DSP—applications in audio, medi-
Super Harvard Architecture—four independent buses for
Code compatible with all other sharc family DSPs
Single-instruction multiple-data (SIMD) computational archi-
Serial ports offer I
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
cal, military, wireless communications, graphics, imaging,
motor-control, and telephony
dual data fetch, instruction fetch, and nonintrusive zero-
overhead I/O
tecture—two 32-bit IEEE floating-point computation units,
each with a multiplier, ALU, shifter, and register file
taneous receive or transmit pins, which support up to 16
transmit or 16 receive channels of audio
S
MULT
8
CONNECT
DAG1
BUS
(PX)
4
32
16
REGISTER
2
8
S support via 8 programmable and simul-
DATA
(PEX)
FILE
DAG2
40-BIT
4
CORE PROCESSOR
32
PM ADDRESS BUS
DM ADDRESS BUS
DM DATA BUS
PM DATA BUS
ALU
BARREL
SHIFTER
TIMER
SEQUENCER
PROGRAM
INSTRUCTION
32
CACHE
48-BIT
32
32
64
64
Figure 1. ADSP-21161N Functional Block Diagram
BARREL
SHIFTER
ALU
ADDR
PROCESSOR PORT
16
REGISTER
ADDR
DATA
(PEY)
FILE
40-BIT
DUAL-PORTED BLOCKS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Integrated peripherals—integrated I/O processor, 1m bit on-
ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit
100 MHz/110 MHz core instruction rate
Single-cycle instruction execution, including SIMD opera-
Up to 660 MFLOPs peak and 440 MFLOPs sustained
225-ball 17 mm 17 mm CSP_BGA package
TWO INDEPENDENT
chip dual-ported SRAM, SDRAM controller, glueless multi-
processing features, and I/O ports (serial, link, external
bus, SPI, and JTAG)
floating-point formats
tions in both computational units
performance
DATA
DUAL-PORTED SRAM
DATA
MULT
DATA
IOD
64
DATA
(MEMORY MAPPED)
I/O PORT
©2009 Analog Devices, Inc. All rights reserved.
DATA BUFFERS
REGISTERS
STATUS, &
CONTROL,
ADDR
IOP
SHARC Processor
ADDR
IOA
18
I/O PROCESSOR
ADSP-21161N
MULTIPROCESSOR
SERIAL PORTS (4)
LINK PORTS (2)
CONTROLLER
SPI PORTS (1)
EXTERNAL PORT
INTERFACE
AND EMULATION
HOST PORT
CONTROLLER
DMA
JTAG TEST
ADDR BUS
DATA BUS
SDRAM
FLAGS
www.analog.com
GPIO
MUX
MUX
12
24
32
16
20
6
8
5
4

Related parts for ADSP-21161NKCAZ100

ADSP-21161NKCAZ100 Summary of contents

Page 1

... SRAM, SDRAM controller, glueless multi- processing features, and I/O ports (serial, link, external bus, SPI, and JTAG) ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats 100 MHz/110 MHz core instruction rate Single-cycle instruction execution, including SIMD opera- ...

Page 2

... ADSP-21161N TABLE OF CONTENTS Summary ............................................................... 1 Revision History ...................................................... 2 General Description ................................................. 3 ADSP-21161N Family Core Architecture .................... 3 ADSP-21161N Memory and I/O Interface Features ....... 5 Development Tools ............................................... 9 Additional Information ........................................ 11 Pin Function Descriptions ....................................... 12 Boot Modes ....................................................... 17 Specifications ........................................................ 18 Operating Conditions .......................................... 18 Electrical Characteristics ....................................... 19 REVISION HISTORY 11/09—Rev Rev. B. Corrected all outstanding document errata. ...

Page 3

... ADSP-2106x on a range of DSP algorithms. Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21161N has instruction cycle time. With its SIMD computational hardware running at 110 MHz, the ADSP-21161N can perform 660 million math opera- tions per second ...

Page 4

... CS D3B HBR HBG SPICLK REDY SPIDS BR6-1 MOSI MISO PA SBTS RESET RSTOUT JTAG 7 Figure 2. System Diagram Rev Page November 2009 2). With the ADSP-21161N’s separate program and CS BOOT ADDR EPROM (OPTIONAL) DATA ADDR MEMORY DATA AND OE PERIPHERALS WE (OPTIONAL) ACK CS RAS CAS ...

Page 5

... The dual-ported memory in combination with three separate on-chip buses allow two data transfers from the core and one from the I/O processor single cycle. On the ADSP-21161N, the memory can be configured as a maximum of 32K words of 32-bit data, 64K words of 16-bit data, 21K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit ...

Page 6

... ADSP-21161N’s internal mem- ory and external memory, external peripherals host processor. DMA transfers can also occur between the ADSP- 21161N’s internal memory and its serial ports, link ports, or the SPI-compatible (Serial Peripheral Interface) port. External bus ...

Page 7

... ADSP-21161N’s external bus with the host bus request (HBR), host bus grant (HBG), and chip select (CS) sig- nals. The host can directly read and write the internal IOP registers of the ADSP-21161N, and can access the DMA channel Rev Page November 2009 ADSP-21161N ...

Page 8

... DMA transfers. Vector interrupt support provides efficient execution of host commands. ADSP-21161N #4 ADSP-21161N #3 ADDR23-0 CLKIN DATA47-16 RESET 3 ID2-0 CONTROL ADSP-21161N #2 CLKIN ADDR23-0 DATA47-16 RESET 2 ID2-0 CONTROL ADSP-21161N #1 BMS ADDR23-0 CLKIN DATA47-16 RESET RD 1 ID2-0 WR ACK MS3-0 SBTS CS HBR HBG REDY BR6-2 BR1 RAS ...

Page 9

... Maintaining a one-to-one correspondence with the tool’s command line switches. Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-21161N processor to monitor and con- trol the target board processor during emulation. The emulator Rev Page November 2009 ...

Page 10

... ADSP-21161N provides full-speed emulation, allowing inspection and modifi- cation of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family ...

Page 11

... ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21161N architecture and functionality. For detailed information on the ADSP-2116x Family core architecture and instruction set, refer to the ADSP-21161 SHARC DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference. 0.10" Rev Page November 2009 ...

Page 12

... IOP DMA parameter registers). The ADSP-21161N inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0 pins maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2–0=00x. ...

Page 13

... BRST is asserted after the initial access of a burst transfer asserted for every cycle after that, except for the last data request cycle (denoted asserted and BRST negated). A keeper latch on the DSP’s BRST pin maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2–0=00x. ...

Page 14

... Bus Master Output multiprocessor system, indicates whether the ADSP-21161N is current bus master of the shared external bus. The ADSP-21161N drives BMSTR high only while it is the bus master single- processor system (ID=000), the processor drives this pin high. This pin is used for debugging purposes. ...

Page 15

... MISO I/O (o/d) SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21161N is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data ADSP-21161N SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master ...

Page 16

... The frequency is determined by the CLKDBL pin. This output is three-stated when the ADSP-21161N is not the bus master or when the host controls the bus (HBG asserted). A keeper latch on the DSP’s CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on the ADSP- 21161N with ID2–0=00x. ...

Page 17

... EPROM (Connect BMS to EPROM chip select (Input) Host Processor (Input) Serial Boot via SPI (Input) Link Port (Input) No Booting. Processor executes from external memory (Input) Reserved CLK_CFG0 Core:CLKIN 0 2:1 1 3:1 0 4:1 0 4:1 1 6:1 0 8:1 Rev Page November 2009 ADSP-21161N CLKIN:CLKOUT 1 1:2 1:2 1:2 ...

Page 18

... ADSP-21161N SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DDINT AV Analog (PLL) Supply Voltage DD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage Low Level Input Voltage IL T Case Operating Temperature CASE 1 Specifications subject to change without notice. 2 Applies to input and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7– ...

Page 19

... DDINHIGH composite average based on a range of low activity code. DDINLOW 18 Idle denotes ADSP-21161N state during execution of IDLE instruction. 19 Characterized, but not tested. 20 Applies to all signal pins. 21 Guaranteed, but not tested. Test Conditions ...

Page 20

... DSP’s internal clock (the clock source for the external port logic and I/O pads). The ADSP-21161N’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’ ...

Page 21

... Using the current specifications ( DDINPEAK DDINHIGH DDINLOW Electrical Characteristics on Page 19 and the current-versus- operation information in Table 8, the programmer can estimate the ADSP-21161N’s internal power supply (V rent for a specific application, according to the following formula: % Peak INPEAK % High INHIGH % Low I - ...

Page 22

... ADSP-21161N Table 8. Operation Types Versus Input Current Operation Peak Activity Instruction Type Multifunction Instruction Fetch Cache 2 Core Memory Access 2 per t CK Internal Memory DMA 1 per 2 t External Memory DMA 1 per external port cycle ( 32) Data bit pattern for core Worst case memory access and DMA 1 The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations ...

Page 23

... The bootstrap Schottky diode is connected between the 1.8 V and 3.3 V power supplies as shown in Figure ADSP-21161N from partially powering the 3.3 V supply. Including a Schottky diode will shorten the delay between the supply ramps and thus prevent damage to the ESD diode Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup) ...

Page 24

... ADSP-21161N Clock Input In systems that use multiprocessing or SBSRAM, CLKDBL can- not be enabled nor can the systems use an external crystal as the CLKIN source. Table 11. Clock Input Parameter Timing Requirements t CLKIN Period CLKIN Width Low CKL 1 t CLKIN Width High CKH t CLKIN Rise/Fall (0.4 V–2.0 V) ...

Page 25

... Applies after the power-up sequence is complete. 2 Only required if multiple ADSP-21161Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21161Ns communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset. ...

Page 26

... ADSP-21161N Interrupts Table 13. Interrupts Parameter Timing Requirements t IRQ2–0 Setup Before CLKIN SIR t IRQ2–0 Hold After CLKIN HIR 2 t IRQ2–0 Pulsewidth IPW 1 Only required for IRQx recognition in the following cycle. 2 Applies only if t and t requirements are not met. SIR ...

Page 27

... Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2. CLKIN t DFOE FLAG11–0 OUT CLKIN FLAG11– DWRFI , FLAG INPUT 100 MHz Min Max Enable 1 Disable 5 t DFO t HFO FLAG OUTPUT t t SFI HFI t HFIWR Figure 20. Flags Rev Page November 2009 ADSP-21161N 110 MHz Min Max DFO DFOD Unit ...

Page 28

... CKOP . SDS. Example System Hold Time Calculation on Page For the second and subsequent cycles of an asynchronous external memory access, the t DSAK SAKC Rev Page November 2009 16. These specifications apply when the ADSP-21161N is 110 MHz Min Max t –0.25t CKOP CCLK 0.75t –11+W ...

Page 29

... ADDRESS MSx, BMS t DARL RD DATA t DSAK t DAAK ACK CLKIN WR, DMAG DRLD SDS t DAD t t HAKC SAKC Figure 21. Memory Read — Bus Master Rev Page November 2009 ADSP-21161N t HDA t DRHA t HDRH t RWR ...

Page 30

... CCLK . CKOP , For the second and subsequent cycles of an asynchronous external memory access, the t DSAK SAKC for calculation of hold times given capacitive and dc loads. Rev Page November 2009 17. These specifications apply when the ADSP-21161N is Max t –0.5t –12+W CKOP CCLK t –0.75t –11+W ...

Page 31

... ADDRESS MSx, BMS t DAWL WR DATA t DAAK ACK CLKIN RD, DMAG t DAWH WDE t DDWH t DSAK t t SAKC Figure 22. Memory Write — Bus Master Rev Page November 2009 ADSP-21161N t DWHA t WWR t DATRWH t DDWR t DWHD HAKC ...

Page 32

... DADDO DRWL DRWL t DDATO Figure 23. Synchronous Read/Write — Bus Master Rev Page November 2009 Synchronous Read/Write — Bus Slave on 33). The slave ADSP-21161N must also meet these (bus Min Max 5.5 1 0.5t +3 CCLK 1 10 1.5 0.25t – ...

Page 33

... Synchronous Read/Write — Bus Slave Use these specifications for ADSP-21161N bus master accesses of a slave’s IOP registers in multiprocessor memory space. The bus master must meet these (bus slave) timing requirements. Table 19. Synchronous Read/Write — Bus Slave Parameter Timing Requirements t Address, BRST Setup Before CLKIN ...

Page 34

... ADSP-21161N Host Bus Request Use these specifications for asynchronous host bus requests of an ADSP-21161N (HBR, HBG). Table 20. Host Bus Request Parameter Timing Requirements t HBG Low to RD/WR/CS Valid HBGRCSV t HBR Setup Before CLKIN SHBRI 1 t HBR Hold After CLKIN HHBRI t HBG Setup Before CLKIN ...

Page 35

... CLKIN HBR HBG (OUT) HBG (IN) HBR REDY (O/D) REDY (A/D) HBG (OUT O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 25. Host Bus Request Rev Page November 2009 ADSP-21161N YTR ...

Page 36

... ADSP-21161N Multiprocessor Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-21161Ns (BRx). Table 21. Multiprocessor Bus Request Parameter Timing Requirements t BRx, Setup Before CLKIN High SBRI t BRx, Hold After CLKIN High HBRI t PA Setup Before CLKIN High SPAI t PA Hold After CLKIN High ...

Page 37

... Asynchronous Read/Write — Host to ADSP-21161N Use these specifications for asynchronous host processor accesses of an ADSP-21161N, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-21161N, the host can drive the RD and WR pins to access the ADSP-21161N’s IOP registers. HBR and HBG are assumed low Table 22 ...

Page 38

... O/D = OPEN DRAIN, A/D = ACTIVE DRIVE t SADRDL t S DAT RDY t t DRDY RDL RDYPRD t S ADW RH t SCS WRL t WWRL t SDATWH t t DRDY WRL RDYPW R Figure 27. Asynchronous Read/Write — Host to ADSP-21161N Rev Page November 2009 t HADRDH t WRWH t HDARW H t DRDHRDY t HADW RH t HCSWRH HDATWH t DWRHRDY ...

Page 39

... CKOP 3 1.5 3 1.5 1.5 0 CKOP t CKOP 4 1.5t –6 CKOP CKOP 4 0.5t –4 CKOP 4 t –5 CKOP Rev Page November 2009 ADSP-21161N Max 0.5t – CKOP – t 12.5 CCLK CKOP CCLK – 0. – CCLK CKOP CCLK 0. CCLK CKOP CCLK ...

Page 40

... ADSP-21161N CLKIN SBTS t MIENA, MEMORY INTERFACE t DATEN DATA t ACKEN ACK CLKIN t CDCEN CLKOUT HBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE) t STSCK t HTSCK t t MIENS, MIENHG t DATTR t ACKTR t MENHBG Figure 28. Three-State Timing — Bus Master, Bus Slave Rev ...

Page 41

... CKOP CCLK 7 –1.5 +2 0.5t – 2+HI CCLK 1 . CKOP + WDR DMARH and t . WDR DMARH for calculation of hold times given capacitive and dc loads. Rev Page November 2009 ADSP-21161N 110 MHz Min Max 3.5 t +4.5 CCLK –7 t – 0.5t CCLK CKOP CKOP t CKOP t +4.5 ...

Page 42

... CLKIN t SDRC DMARx DMAGx TRANSFERS BETWEEN ADSP-21161N INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2116x TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-21161N) TRANSFERS BETWEEN EXTERNAL DEVICE AND 1 EXTERNAL MEMORY (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ADDRESS ...

Page 43

... SDRAM Interface — Bus Master Use these specifications for ADSP-21161N bus master accesses of SDRAM: Table 26. SDRAM Interface — Bus Master Parameter Timing Requirements t Data Setup Before SDCLK SDSDK t Data Hold After SDCLK HDSDK Switching Characteristics t First SDCLK Rise Delay After CLKIN ...

Page 44

... ADSP-21161N CLKIN t DSDK1 SDCLK t SDSDK DATA(IN) t DCADSDK t SDENSDK DATA(OUT) t DCADSDK 1 CMND ADDR (OUT) t SDCEN 1 CMND (OUT) ADDR (OUT) t SDAEN CLKIN t SDSDKEN SDCLK CLKOUT SDCLK (IN) 2 CMND (IN) COMMAND = SDCKE, MSx, RAS, CAS, SDWE, DQM, AND SDA10 COMMAND = SDCKE, RAS, CAS, AND SDWE. ...

Page 45

... The setup and hold skew times shown below are calculated to include only one tester guardband. ADSP-21161N Setup Skew = 1.5 ns max ADSP-21161N Hold Skew = 1.5 ns max ). Hold skew is the Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port. – ...

Page 46

... ADSP-21161N Table 29. Link Ports — Transmit Parameter Timing Requirements t LACK Setup Before LCLK High SLACH t LACK Hold After LCLK High HLACH Switching Characteristics t Data Delay After LCLK High DLDCH t Data Hold After LCLK High HLDCH t LCLK Width Low LCLKTWL t LCLK Width High ...

Page 47

... SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register. 3 SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register Min Rev Page November 2009 ADSP-21161N Min Max Unit 3 1 CCLK Min Max Unit 8 ns 0.5t ...

Page 48

... ADSP-21161N Table 34. Serial Ports —– Enable and Three-State Parameter Switching Characteristics t Data Enable from External Transmit SCLK DDTEN t Data Disable from External Transmit SCLK DDTTE t Data Enable from Internal Transmit SCLK DDTIN t Data Disable from Internal Transmit SCLK DDTTI 1 Referenced to drive edge. ...

Page 49

... DATA TRANSMIT — EXTERNAL CLOCK DRIVE EDGE SCLK t t HFSI HOFSE FS t HDTE D A SCLK SCLK t DDTIN Figure 33. Serial Ports Rev Page November 2009 ADSP-21161N SAMPLE EDGE t SCLKW t DFSE t t SFSE HFSE t t HDRE SDRE SAMPLE EDGE t SCLKW t DFSE t t SFSE ...

Page 50

... ADSP-21161N SCLK SCLK EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE DDTENFS HDTE/I 1ST BIT t DDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE DDTENFS HDTE/I 1ST BIT 2ND BIT t DDTLFSE Figure 34. Serial Ports — External Late Frame Sync Rev ...

Page 51

... HDSPIDM MSB MSB VALID MSB LSB VALID Figure 35. SPI Interface Protocol — Master Switching and Timing Rev Page November 2009 ADSP-21161N 100 MHz 110 MHz Max Min Max +10 0.5t +10 CCLK +1 0.5t +1 CCLK 8t –4 CCLK 4t –4 CCLK 4t –4 CCLK CCLK 3t CCLK t –3 ...

Page 52

... ADSP-21161N Table 37. SPI Interface Protocol — Slave Switching and Timing Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 t Last SPICLK Edge to SPIDS Not Asserted ...

Page 53

... SPICLK ( (INPUT SPICLK ( (INPUT MISO (OUTPUT) t CPHASE = MOSI (INPUT MISO MSB (OUTPUT) CPHASE = 0 MOSI MSB VALID (INPUT) Figure 36. SPI Interface Protocol — Slave Switching and Timing MSB MSB VALID LSB VALID LSB LSB VALID Rev Page November 2009 ADSP-21161N LSB ...

Page 54

... ADSP-21161N JTAG Test Access Port and Emulation Table 38. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK Low SSYS ...

Page 55

... OUTPUT DRIVE CURRENTS Figure 38 shows typical I-V characteristics for the output driv- ers of the ADSP-21161N. The curves represent the current drive capability of the output drivers as a function of output voltage 3.47V, –40°C DDEXT 3.3V, +25°C DDEXT –10 –20 – 3.47V, –40°C DDEXT – ...

Page 56

... Thermal Characteristics The ADSP-21161N is packaged in a 225-ball chip scale package ball grid array (CSP_BGA). The ADSP-21161N is specified for a case temperature (T specification is not exceeded, a heatsink and/or an air flow source may be used. Use the center block of ground pins (CSP_BGA balls: F6-10, G6-10, H6-10, J6-10, K6-10) to provide thermal pathways to the printed circuit board’ ...

Page 57

... DDINT K09 V DDEXT K10 V DDINT K11 V DDEXT K12 CAS K13 DATA20 K14 DATA16 K15 DATA18 Rev Page November 2009 ADSP-21161N Ball Number Ball Name Ball Number C01 TDO D01 C02 TCK D02 C03 FLAG11 D03 C04 MISO D04 C05 SCLK0 D05 ...

Page 58

... ADSP-21161N Table 40. 225-Ball CSP_BGA Ball Assignments (Continued) Ball Name Ball Number Ball Name ADDR14 N01 ADDR13 ADDR15 N02 ADDR9 ADDR10 N03 ADDR8 ADDR5 N04 ADDR4 ADDR1 N05 MS2 MS0 N06 SBTS BR5 N07 BR4 BR2 N08 BR1 BRST N09 SDCLK1 SDCKE ...

Page 59

... Standard. Table 41. BGA Data for Use with Surface-Mount Design Package 225-Ball CSP_BGA (BC-225-1) ORDERING GUIDE Model Temperature Range ADSP-21161NKCA-100 ADSP-21161NCCA-100 – +105 C 2 ADSP-21161NKCAZ100 ADSP-21161NCCAZ100 – +105 C 2 ADSP-21161NYCAZ110 – +125 C 1 Referenced temperature is case temperature indicates RoHS compliant package. 17.20 17 ...

Page 60

... ADSP-21161N © 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02935-0-11/09 (B) Rev Page November 2009 ...

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