CMOS ISP EEPLD, SMD, 2032, PLCC44

ISPLSI2032E-110LJ44

Manufacturer Part NumberISPLSI2032E-110LJ44
DescriptionCMOS ISP EEPLD, SMD, 2032, PLCC44
ManufacturerLATTICE SEMICONDUCTOR
ISPLSI2032E-110LJ44 datasheet
 


Specifications of ISPLSI2032E-110LJ44

No. Of Macrocells32No. Of I/o's34
Propagation Delay10nsGlobal Clock Setup Time7.5ns
Frequency110MHzSupply Voltage Range4.75V To 5.25V
Operating Temperature Range0°C To +70°C  
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Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
with ispLSI 2032 Devices
2
®
• HIGH PERFORMANCE E
CMOS
TECHNOLOGY
f
max = 225 MHz Maximum Operating Frequency
t
pd = 3.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)
Supports Mixed Voltage Systems
— PCI Compatible Outputs (48-Pin Package Only)
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032e_04
ispLSI
In-System Programmable
SuperFAST™ High Density PLD
Functional Block Diagram
Global Routing Pool
A0
(GRP)
A1
D Q
D Q
Logic
A2
GLB
Array
D Q
D Q
A3
Description
The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
1
®
2032E
A7
A6
A5
A4
0139Bisp/2000
January 2002

ISPLSI2032E-110LJ44 Summary of contents

  • Page 1

    ... Optimized Global Routing Pool Provides Global Interconnectivity Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

  • Page 2

    Functional Block Diagram Figure 1. ispLSI 2032E Functional Block Diagram GOE 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 ...

  • Page 3

    Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...

  • Page 4

    ... Available in 48-pin package only. 6. Maximum I varies widely with specific device configuration and operating frequency. Refer to the CC Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I Specifications ispLSI 2032E Figure 2. Test Load GND to 3 ...

  • Page 5

    External Timing Parameters TEST 2 PARAMETER # 4 COND Data Prop. Delay, 4PT Bypass, ORP Bypass pd1 Data Prop. Delay pd2 f max A 3 Clk Frequency with Int. Feedback f – 4 Clk ...

  • Page 6

    External Timing Parameters TEST 2 PARAMETER # 4 COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f – 4 Clock ...

  • Page 7

    Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...

  • Page 8

    Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...

  • Page 9

    Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic ...

  • Page 10

    Power Consumption Power consumption in the ispLSI 2032E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax 150 140 130 ...

  • Page 11

    Pin Description 44-PIN PLCC PIN NUMBERS NAME I I/O 3 15, 16, 17, 18, I I/O 7 19, 20, 21, 22, I I/O 11 25, 26, 27, 28, I I/O 15 29, ...

  • Page 12

    Pin Configuration ispLSI 2032E 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I VCC BSCAN 1 TDI/IN 0 I/O 0 I Pins have dual function capability pins are not to ...

  • Page 13

    Pin Configuration ispLSI 2032E 48-Pin TQFP Pinout Diagram I/O 28 I/O 29 I VCC BSCAN 1 TDI/IN 0 I/O 0 I/O 1 I/O 2 GND 1. Pins have dual function capability pins are not ...

  • Page 14

    Part Number Description ispLSI 2032E Device Family Device Number Speed f 225 = 225 MHz max f 200 = 200 MHz max f 180 = 180 MHz max f 135 = 135 MHz max f 110 = 110 MHz max ...