ISPLSI2032E-110LJ44 LATTICE SEMICONDUCTOR, ISPLSI2032E-110LJ44 Datasheet - Page 9

• Manufacturer Part Number: ISPLSI2032E-110LJ44
• Description: CMOS ISP EEPLD, SMD, 2032, PLCC44
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI2032E-110LJ44

• No. Of Macrocells: 32
• No. Of I/o's: 34
• Propagation Delay: 10ns
• Global Clock Setup Time: 7.5ns
• Frequency: 110MHz
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C

Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L
Derivations of
ispLSI 2032E Timing Model
GOE 0
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
t
t
su
h
co
2.7
2.3
6.8
I/O Delay
=
=
=
=
=
=
=
=
=
=
=
=
#21
#20
t
su,
I/O Cell
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
Reg 4 PT Bypass
t
#33, 34,
XOR Delays
orp +
Control
PTs
Feedback
#25, 26, 27
t
grp +
20 PT
35
t
grp +
#24
Comb 4 PT Bypass #23
t
9
ob)
RE
OE
CK
t
ptck(min))
t
20ptxor)
Specifications ispLSI 2032E
GLB
GLB Reg Bypass
D
RST
Table 2-0042/2032E
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2032E
#38,
#39
I/O Cell
(Output)
I/O Pin