LPC2378FBD144 NXP Semiconductors, LPC2378FBD144 Datasheet - Page 32

MCU 32BIT ARM7, 10/100, USB, CAN

LPC2378FBD144

Manufacturer Part Number
LPC2378FBD144
Description
MCU 32BIT ARM7, 10/100, USB, CAN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC2378FBD144

Core Size
32bit
No. Of I/o's
104
Program Memory Size
512KB
Ram Memory Size
58KB
Cpu Speed
72MHz
Oscillator Type
External, Internal
No. Of Timers
4
No. Of Pwm Channels
6
Digital Ic Case
RoHS Compliant
Controller Family/series
LPC23xx
Rohs Compliant
Yes

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NXP Semiconductors
LPC2377_78
Product data sheet
7.25.1.2 Main oscillator
7.25.1.3 RTC oscillator
7.25.2 PLL
7.25.3 Wake-up timer
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can
be boosted to a higher frequency, up to the maximum CPU operating frequency, by the
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to
The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the
RTC oscillator can be used to drive the PLL and the CPU.
The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value
‘N’, which may be in the range of 1 to 256. This input division provides a wide range of
output frequencies from the same input frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only. The program must configure and activate the PLL,
wait for the PLL to lock, then connect to the PLL as a clock source.
The LPC2377/78 begin operation at power-up and when awakened from Power-down and
Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This
allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down and Deep power-down
modes, any wake-up of the processor from Power-down mode makes use of the wake-up
Timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some event caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
All information provided in this document is subject to legal disclaimers.
Section 7.25.2
Rev. 5 — 17 June 2010
for additional information.
Single-chip 16-bit/32-bit microcontrollers
LPC2377/78
© NXP B.V. 2010. All rights reserved.
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