CA3054

Manufacturer Part NumberCA3054
DescriptionTransistor Array IC
ManufacturerIntersil
CA3054 datasheets
 


Specifications of CA3054

Amplifier Case StyleSOICNo. Of Pins14
No. Of Transistors6Mounting TypeSurface Mount
Package / Case14-SOIC  
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Data Sheet
Dual Independent Differential Amp for
Low Power Applications from DC to
120MHz
The CA3054 consists of two independent differential
amplifiers with associated constant current transistors on a
common monolithic substrate. The six NPN transistors which
comprise the amplifiers are general purpose devices which
exhibit low 1/f noise and a value of f
in excess of 300MHz.
T
These feature make the CA3054 useful from DC to 120MHz.
Bias and load resistors have been omitted to provide
maximum application flexibility.
The monolithic construction of the CA3054 provides close
electrical and thermal matching of the amplifiers. This
feature makes these devices particularly useful in dual
channel applications where matched performance of the two
channels is required.
Ordering Information
PART NUMBER
TEMP.
(BRAND)
RANGE (°C)
PACKAGE
CA3054M96
0 to 85
14 Ld SOIC
(3054)
Tape and Reel
CA3054MZ
0 to 85
14 Ld SOIC
(CA3054MZ)
(Pb-free)
CA3054MZ96
0 to 85
14 Ld SOIC Tape
(CA3054MZ)
and Reel (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
September 22, 2005
Features
• Two Differential Amplifiers on a Common Substrate
• Independently Accessible Inputs and Outputs
• Maximum Input Offset Voltage . . . . . . . . . . . . . . . . . ±5mV
• Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Dual Sense Amplifiers
• Dual Schmitt Triggers
• Multifunction Combinations
- RF/Mixer/Oscillator; Converter/IF
• IF Amplifiers (Differential and/or Cascode)
• Product Detectors
• Doubly Balanced Modulators and Demodulators
PKG.
• Balanced Quadrature Detectors
DWG. #
• Cascade Limiters
M14.15
• Synchronous Detectors
M14.15
• Pairs of Balanced Mixers
• Synthesizer Mixers
M14.15
• Balanced (Push-Pull) Cascode Amplifiers
Pinout
SUBSTRATE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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1-888-INTERSIL or 1-888-468-3774
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Harri Corporation 1998. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA3054
FN388.6
CA3054 (SOIC)
TOP VIEW
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CA3054 Summary of contents

  • Page 1

    ... T These feature make the CA3054 useful from DC to 120MHz. Bias and load resistors have been omitted to provide maximum application flexibility. The monolithic construction of the CA3054 provides close electrical and thermal matching of the amplifiers ...

  • Page 2

    ... NOTES: 1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors. 2. θ ...

  • Page 3

    ... Noise Figure for Single Transistor Gain Bandwidth Product for Single Transistor (Figure 14) Admittance Characteristics; Differential Circuit Configuration (For Each Amplifier) Forward Transfer Admittance (Figure 15) Input Admittance (Figure 16) Output Admittance (Figure 17) Reverse Transfer Admittance (Figure 18) 3 CA3054 SYMBOL TEST CONDITIONS 50µ ...

  • Page 4

    ... Noise Figure Test Circuits V = 0.3V IN RMS 10µ SIGNAL SOURCE 0.5kΩ 0.5kΩ 0.1µF FIGURE 1. COMMON MODE REJECTION RATIO TEST SETUP V = 1mV IN RMS SIGNAL SOURCE 4 CA3054 SYMBOL TEST CONDITIONS 3V 1MHz 21 CB Total Stage 3V 1MHz 11 CB Total Stage 3V 1MHz 22 CB Total Stage I Y ...

  • Page 5

    ... FIGURE 5. INPUT BIAS CURRENT vs COLLECTOR CURRENT 0.75 0.50 0. 100 125 -75 NOTE: For CA3054 use data from 0°C to 85°C only. FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR 25° 1.0 2 0.1 1 0.01 0 0.01 10 FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED = 3V 1 ...

  • Page 6

    ... FIGURE 12. TWO STAGE VOLTAGE GAIN CHARACTERISTIC 25°C A 1000 900 800 700 600 500 400 300 200 100 COLLECTOR CURRENT (mA) FIGURE 14. GAIN BANDWIDTH PRODUCT (f CURRENT 6 CA3054 (Continued) 100 1kHz 75 SIGNAL INPUT = 10mV -25 - FIGURE 11. SINGLE STAGE VOLTAGE GAIN CHARACTERISTIC 100 1kHz T = 25°C A RMS ...

  • Page 7

    ... FREQUENCY (MHz) FIGURE 18. REVERSE TRANSFER ADMITTANCE (Y FREQUENCY CASCODE CONFIGURATION ≅ I (STAGE) 2.5mA 25° 0.1 1 FREQUENCY (MHz) FIGURE 20. INPUT ADMITTANCE (Y 7 CA3054 (Continued) DIFFERENTIAL CONFIGURATION 0.4 0 100 0.1 ) FIGURE 17. OUTPUT ADMITTANCE (Y 11 1000 80 100 60 CASCODE CONFIGURATION ...

  • Page 8

    ... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 CA3054 (Continued) 100 CASCODE CONFIGURATION ≅ ...