CDB4382A

Manufacturer Part NumberCDB4382A
DescriptionEval Bd 114dB 192kHz 8Chn DAC W/DSD Supt
ManufacturerCirrus Logic Inc
CDB4382A datasheets
 


Specifications of CDB4382A

Number Of Dac's8Number Of Bits24
Outputs And Type8, Single EndedSampling Rate (per Second)192k
Data InterfaceSerialDac TypeVoltage
Voltage Supply SourceAnalog and DigitalOperating Temperature-40°C ~ 85°C
Utilized Ic / PartCS4382ADescription/functionAudio D/A
Operating Supply Voltage5 VProductAudio Modules
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantFor Use With/related ProductsCS4382A
Other names598-1524  
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Download datasheet (982Kb)Embed
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114 dB, 192 kHz 8-Channel D/A Converter
Features
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
®
Direct Stream Digital
(DSD
On-chip 50 kHz Filter
Matched PCM and DSD Analog Output Levels
Selectable Digital Filters
Volume Control with 1 dB Step Size and Soft
Ramp
Low Clock-jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
C o n tro l & S erial A u d io P o rt
S u p p lies = 1.8 V to 5 V
H ard w are Mo d e o r
2
I
C /S P I S o ftw are Mo d e
C o n tro l D ata
R es et
P C M S erial
A u d io In p u t
D S D A u d io
In p u t
http://www.cirrus.com
Description
The CS4382A is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
1 dB step size volume control, ATAPI channel mixing,
selectable fast and slow digital interpolation filters fol-
lowed by an oversampled, multi-bit delta-sigma
modulator which includes mismatch shaping technolo-
gy that eliminates distortion due to capacitor mismatch.
Following this stage is a multi-element switched capac-
itor stage and low-pass filter with differential analog
outputs.
) Mode
The CS4382A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an in-
termediate decimation stage. The CS4382A is available
in a 48-pin LQFP package in both Commercial (-40°C to
+85°C) and Automotive grades (-40°C to +105°C). The
CDB4382A Customer Demonstration board is also
available for device evaluation and implementation sug-
gestions. Please see
for complete details.
The CS4382A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers,
processors, sound cards, and automotive audio
systems.
D ig ital S u p p ly = 2.5 V
R e giste r/H a rdwa re
C onfigura tion
V olume
Multi-bit ∆Σ
D igita l
C ontrols
F ilte rs
Modula tors
8
D S D P roce ssor
-50 kH z filte r
Copyright © Cirrus Logic, Inc. 2009
(All Rights Reserved)
CS4382A
“Ordering Information” on page 48
digital
TV’s,
mixing
consoles,
A n alo g S u p p ly = 5 V
Inte rna l V olta ge
R e fe re nce
S witch-C a p
D ifferen tial
8
D A C a nd
O u tp u ts
A na log F ilte rs
8
E xte rna l Mute
Mu te S ig n als
C ontrol
2
effects
JAN '09
DS618F2

CDB4382A Summary of contents

  • Page 1

    ... The CS4382A is available in a 48-pin LQFP package in both Commercial (-40°C to +85°C) and Automotive grades (-40°C to +105°C). The CDB4382A Customer Demonstration board is also available for device evaluation and implementation sug- gestions. Please see for complete details. ...

  • Page 2

    TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ............................................................. 9 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ........................................................... 10 ...

  • Page 3

    Digital Interface Format (DIF) ................................................................................................ 34 6.3 Mode Control 3 (Address 03h) ....................................................................................................... 35 6.3.1 Soft Ramp and Zero Cross Control (SZC) ............................................................................ 35 6.3.2 Single Volume Control (SNGLVOL) ...................................................................................... 36 6.3.3 Soft Volume Ramp-Up After Error (RMP_UP) ...................................................................... ...

  • Page 4

    LIST OF FIGURES Figure 1.Serial Audio Interface Timing ...................................................................................................... 15 Figure 2.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16 Figure 3.Control Port Timing - I²C Format ................................................................................................. 17 Figure 4.Control Port Timing - SPI Format ................................................................................................ 18 Figure ...

  • Page 5

    LIST OF TABLES Table 1. Common Clock Frequencies ....................................................................................................... 21 Table 2. Digital Interface Format, Stand-Alone Mode Options .................................................................. 22 Table 3. Mode Selection, Stand-Alone Mode Options .............................................................................. 22 Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ........................................................... 22 ...

  • Page 6

    PIN DESCRIPTION LRCK(DSD_EN) Pin Name # VD 4 Digital Power (Input) - Positive power supply for the digital section. 5 GND Ground (Input) - Ground reference. Should be connected to analog ground. 31 MCLK 6 Master Clock (Input) - ...

  • Page 7

    Pin Name # AOUTA1 +,- 39, 40 AOUTB1 +,- 38, 37 AOUTA2 +,- 35, 36 AOUTB2 +,- 34, 33 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the AOUTA3 +,- 29, 30 Analog Characteristics ...

  • Page 8

    CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Serial Data Port Interface Power Ambient Operating Temperature (power applied) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages ...

  • Page 9

    DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) Test Conditions (unless otherwise specified VLS = VLC = 2 input sine wave ; Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as ...

  • Page 10

    DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) Test Conditions (unless otherwise specified 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1. 2. ...

  • Page 11

    POWER AND THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply Current (Note 4) (Note 5) (Note 6) Power-down State (all supplies) Power Dissipation (Note 4) Package Thermal Resistance Power Supply Rejection Ratio (Note 7) Notes: 4. Current consumption increases with increasing ...

  • Page 12

    COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. See Note 12. Parameter Combined ...

  • Page 13

    COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) Parameter Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response Stop Band Stop-band Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) Double-Speed Mode - 96 kHz Passband (Note ...

  • Page 14

    DIGITAL CHARACTERISTICS Parameters Input Leakage Current Input Capacitance High-level Input Voltage Low-level Input Voltage Low-level Output Voltage (I = -1.2 mA) OL Maximum MUTEC Drive Current MUTEC High-level Output Voltage MUTEC Low-level Output Voltage 13. Any pin except supplies. Transient ...

  • Page 15

    SWITCHING CHARACTERISTICS - PCM (Inputs: Logic 0 = GND, Logic 1 = VLS, C Parameters RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate - LRCK LRCK Duty Cycle SCLK Duty Cycle SCLK High Time SCLK ...

  • Page 16

    SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VLS; C Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising ...

  • Page 17

    SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock ...

  • Page 18

    SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling ...

  • Page 19

    TYPICAL CONNECTION DIAGRAM +2.5 V PCM Digital Audio Source +1 DSD Audio Source Micro- Controller +1 Note: Necessary for I control port operation Figure 5. Typical Connection Diagram, Software Mode DS618F2 ...

  • Page 20

    VLS PCM Digital Audio Source +1 DSD Audio Source Stand-Alone Configuration +1 Figure 6. Typical Connection Diagram, Hardware Mode 20 +2 µF 0.1 µ AOUTA1+ ...

  • Page 21

    APPLICATIONS The CS4382A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48, 44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data ...

  • Page 22

    M1 M0 (DIF1) (DIF0) Left-justified 24-bit data 0 0 I² 24-bit data 0 1 Right-justified, 16-bit Data 1 0 Right-justified, 24-bit Data 1 1 Table 2. Digital Interface Format, Stand-Alone Mode Options M3 M2 (DEM) Single-speed ...

  • Page 23

    Digital Interface Formats The serial port operates as a slave and supports the I²S, Left-justified, and Right-justified digital interface formats with varying bit depths from shown in rising edge. Left Channel LRCK SCLK SDINx +5 ...

  • Page 24

    LRCK Left Channel SCLK SDINx clocks Figure 11. Format 4 - Right-Justified 20-bit Data LRCK Left Channel SCLK SDINx ...

  • Page 25

    In Software Mode, the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz kHz are selected via the de-emphasis control bits. In Hardware Mode, only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the ...

  • Page 26

    ... DAC. If desired, all supply pins with similar voltage ratings may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. Notes: All decoupling capacitors should be referenced to analog ground. The CDB4382A evaluation board demonstrates the optimum layout and power supply arrangements. 4.10 Analog Output and Filtering The application note “ ...

  • Page 27

    AOUT+ AOUT- Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp 4.11 Mute Control The Mute Control pins go active during power-up initialization, muting the MCLK-to-LRCK ratio is in- correct. These pins are intended to be used as control ...

  • Page 28

    Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min- imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ...

  • Page 29

    Recommended Procedure for Switching Operational Modes For systems where the absolute minimum in clicks and pops is required recommended that the MUTE bits are set prior to changing significant DAC functions (such as changing sample rates or ...

  • Page 30

    I²C Read To read from the device, follow the procedure below while adhering to the Control Port Switching Speci- fications. 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must ...

  • Page 31

    If the INCR bit is set to 0 and further SPI writes to other registers are desired necessary to bring CS high, and follow the procedure detailed from step further writes to other registers ...

  • Page 32

    REGISTER QUICK REFERENCE Addr Function 7 01h Mode Control 1 CPEN 0 default 02h Mode Control 2 Reserved 0 default 03h Mode Control 3 SZC1 1 default 04h Filter Control Reserved 0 default 05h Invert Control INV_B4 0 default ...

  • Page 33

    REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted. 6.1 Mode Control 1 (Address 01h CPEN FREEZE MCLKDIV 0 0 6.1.1 Control Port Enable (CPEN) Default = 0 ...

  • Page 34

    Power Down (PDN) Default = Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The ...

  • Page 35

    DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required master clock-to-DSD-data-rate is defined by the Digital Interface Format pins. DIF2 DIF1 DIFO ...

  • Page 36

    Single Volume Control (SNGLVOL) Default = Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is ...

  • Page 37

    Mutec Pin Control (MUTEC) Default = Two Mute control signals 1 - Single mute control signal on MUTEC1 Function: Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ...

  • Page 38

    Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is per- formed. Loss of ...

  • Page 39

    ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 ...

  • Page 40

    Functional Mode (FM) Default = Single-Speed Mode ( kHz sample rates Double-Speed Mode (50 to 100 kHz sample rates Quad-Speed Mode (100 to 200 kHz sample rates Direct ...

  • Page 41

    Volume Control (XX_VOL) Default = 0 (No attenuation) Function: The Digital Volume Control registers allow independent control of the signal levels increments from 0 to -127 dB. Volume settings are decoded as shown in mented as ...

  • Page 42

    FILTER PLOTS 0 −20 −40 −60 −80 −100 −120 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) Figure 20. Single-Speed (fast) Stopband Rejection 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 ...

  • Page 43

    Frequency(normalized to Fs) Figure 26. Single-Speed (slow) Transition Band (detail 100 120 0.4 0.5 0.6 0.7 Frequency(normalized ...

  • Page 44

    Frequency(normalized to Fs) Figure 32. Double-Speed (slow) Stopband Rejection 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized ...

  • Page 45

    Frequency(normalized to Fs) Figure 38. Quad-Speed (fast) Transition Band (detail 100 120 0.1 0.2 0.3 0.4 0.5 ...

  • Page 46

    PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically kHz), including distortion components. ...

  • Page 47

    PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING D1 D DIM MIN A --- A1 0.002 B 0.007 D 0.343 D1 0.272 E 0.343 E1 0.272 e* 0.016 L 0.018 µ 0.000° DS618F2 ∝ L INCHES ...

  • Page 48

    ... How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters , by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4382A data sheet, available at 3. Design Notes for a 2-Pole Filter with Differential Input , by Steven Green. Cirrus Logic Application Note AN48. 4. The I² ...

  • Page 49

    HISTORY Release Updated output impedance spec in PP1 Improved interchannel isolation spec in PP2 Corrected package type. Corrected register description in Added note to “Digital Interface Format (DIF)” on page Added PCM mode format changeable in reset only to ...

  • Page 50

    Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this ...