CS4382-KQ Cirrus Logic Inc, CS4382-KQ Datasheet - Page 27

• Manufacturer Part Number: CS4382-KQ
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4382-KQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Channels: 8
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5. APPLICATIONS
5.1
As with any high resolution converter, the CS4382
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figures 5 & 6 show the recommended power ar-
rangement with VA, VD, VLS and VLC connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be placed on each supply pin (see Section 1 for rec-
ommended voltages).
5.2
The CS4382 operates in one of three oversampling
modes based on the input sample rate. Mode selec-
tion is determined by the M3 and M2 pins in Stand-
Alone mode or the FM bits in Control Port mode.
Single-Speed mode supports input sample rates up
to 50 kHz and uses a 128x oversampling ratio.
Double-Speed mode supports input sample rates up
to 100 kHz and uses an oversampling ratio of 64x.
Quad-Speed mode supports input sample rates up
to 200 kHz and uses an oversampling ratio of 32x.
5.3
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and VQ
will remain low.
2. Bring RST high. The device will remain in a low
power state with VQ low and will initiate the
Stand-Alone power-up sequence. The control port
will be accessible at this time. If Control Port oper-
ation is desired, write the CPEN bit prior to the
completion of the Stand-Alone power-up se-
quence, approximately 512 LRCK cycles in Sin-
Grounding and Power Supply
Decoupling
Oversampling Modes
Recommended Power-up Sequence
gle-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode). Writing this bit will halt the Stand-
Alone power-up sequence and initialize the control
port to its default settings. The desired register set-
tings can be loaded while keeping the PDN bit set
to 1.
3. If Control Port Mode is selected via the CPEN
bit, set the PDN bit to 0 which will initiate the pow-
er-up sequence.
5.4
The application note “Design Notes for a 2-Pole
Filter with Differential Input” discusses the sec-
ond-order Butterworth filter and differential to sin-
gle-ended converter which was implemented on the
CS4382 evaluation board, CDB4382, as seen in
Figure 42. The CS4382 does not include phase or
amplitude compensation for an external filter.
Therefore, the DAC system phase and amplitude
response will be dependent on the external analog
circuitry.
5.5
To accommodate the increasingly complex re-
quirements of digital audio systems, the CS4382
incorporates selectable interpolation filters for each
mode of operation. A “fast” and a “slow” roll-off
filter is available in each of Single, Double, and
Quad Speed modes. These filters have been de-
signed to accommodate a variety of musical tastes
and styles. The FILT_SEL bit is used to select
which filter is used (see the control port section for
more details).
When in stand-alone mode, only the “fast” roll-off
filter is available.
Filter specifications can be found in Section 1, and
filter response plots can be found in Figures 9 to 32.
Analog Output and Filtering
Interpolation Filter
CS4382
27