CS4382-KQ Cirrus Logic Inc, CS4382-KQ Datasheet - Page 28

• Manufacturer Part Number: CS4382-KQ
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4382-KQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Channels: 8
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.6
The CS4382 has two serial clock and two left/right
clock inputs. The SDINxCLK bits in the control
port allow the user to set which SCLK/LRCK pair
is used to latch the data for each SDINx pin. The
clocks applied to LRCK1 and LRCK2 must be de-
rived from the same MCLK and must be exact fre-
quency multiples of each other as specified in the
“Switching Characteristics” table on page 8. When
using both SCLK1/LRCK1 and SCLK2/LRCK2, if
either SCLK/LRCK pair loses synchronization
then both SCLK/LRCK pairs will go through a re-
time period where the device is re-evaluating clock
ratios. During the retime period all DAC pairs are
temporarily inactive, outputs are muted, and the
mute control pins will go active according to the
MUTEC register.
If unused, SCLK2 and LRCK2 should be tied static
low and SDINx bits should all be set to
SCLK1/LRCK1.
In stand-alone mode all DAC pairs use SCLK1 and
LRCK1 for timing and SCLK2/LRCK2 should be
tied to ground.
5.7
In stand-alone mode, DSD operation is selected by
holding DSD_EN(LRCK1) high and applying the
DSD data and clocks to the appropriate pins. The
M2:0 pins set the expected DSD rate and MCLK
ratio.
In control-port mode the FM bits set the device into
DSD mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected
DSD rate and MCLK ratio.
During DSD operation, the PCM related pins
should either be tied low or remain active with
clocks (except LRCK1 in Stand-Alone mode).
When the DSD related pins are not being used they
should either be tied static low, or remain active
with clocks (except M3 in Stand-Alone mode).
28
Clock Source Selection
Using DSD mode
6. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The CS4382 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written from register 01h to 08h and then from
09h and 11h, allowing block reads or writes of suc-
cessive registers in two separate sections (the
counter will not auto-increment to register 09h
from register 08h).
6.1
On the CS4382 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
is done by performing a I
control port is enabled, these pins are dedicated to
control port functionality.
To prevent audible artifacts the CPEN bit (see Sec-
tion 3.1.1) should be set prior to the completion of
the Stand-Alone power-up sequence, approximate-
ly 1024 LRCK cycles. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; how-
ever, setting this bit after the Stand-Alone power-
up sequence has completed can cause audible arti-
facts.
6.2
The control port has 2 formats: SPI and I
the CS4382 operating as a slave device.
If I
to VLC or GND. If the CS4382 ever detects a high
2
C operation is desired, AD0/CS should be tied
Enabling the Control Port
Format Selection
2
C or SPI write. Once the
CS4382
2
C, with