EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet

32-Bit Microcontroller IC

EP9315-IBZ

Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-IBZ

Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1263

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Quantity
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EP9315-IBZ
Manufacturer:
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EP9315-IBZ
Manufacturer:
CIRRUS
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EP9315-IBZ
Manufacturer:
Cirrus Logic Inc
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EP93XX
®
ARM
9 Embedded Processor Family
EP93xx
Use r ’s Gu id e
©
Copyright 2007 Cirrus Logic, Inc.
SEP 2007
DS785UM1
http://www.cirrus.com

Related parts for EP9315-IBZ

EP9315-IBZ Summary of contents

Page 1

ARM 9 Embedded Processor Family EP93xx Use r ’ © Copyright 2007 Cirrus Logic, Inc. EP93XX DS785UM1 SEP 2007 ...

Page 2

Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document ...

Page 3

Contents Chapter Figures ...

Page 4

EP93xx User’s Guide 2.3.2 AHB-to-APB Bridge .......................................................................................................2-12 2.3.2.1 Function and Operation of the AHB-to-APB Bridge.....................................2-12 2.3.3 APB Slave .....................................................................................................................2-13 2.3.4 Register Definitions .......................................................................................................2-13 2.3.5 Memory Map..................................................................................................................2-16 2.3.6 Internal Register Map ....................................................................................................2-17 2.3.6.1 Memory Access Rules .................................................................................2-17 Chapter 3. MaverickCrunch Co-Processor ...

Page 5

Synchronous Memory Operation.....................................................................................4-7 Chapter 5. System Controller ............................................................................... 5-1 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

EP93xx User’s Guide 7.4.8.6 FRAME_CNTx timing ..................................................................................7-16 7.4.8.7 Grayscale Look-Up Table (GrySclLUT) .......................................................7-17 7.4.8.8 GrySclLUT Timing Diagram .........................................................................7-18 7.4.9 Hardware Cursor ...........................................................................................................7-24 7.4.9.1 Registers Used for Cursor ...........................................................................7-26 7.4.10 Video Timing................................................................................................................7-28 7.4.10.1 Setting the Video Memory Parameters......................................................7-31 7.4.10.2 PixelMode ..................................................................................................7-32 ...

Page 7

Block Copy Function......................................................................................................8-18 8.6.4.1 Example of Block Copy................................................................................8-21 8.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

EP93xx User’s Guide Chapter 10. DMA Controller................................................................................ 10-1 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

... Registers .11-11 Chapter 12. Static Memory Controller ............................................................... 12-1 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 12.2 Static Memory Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2 12.3 PCMCIA Interface (EP9315 Processor Only .12-5 12.4 PC Card Memory-Mode Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8 12.5 PC Card Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8 12.6 Registers .12-10 12.6.1 Bank Configuration Registers....................................................................................12-10 12 ...

Page 10

EP93xx User’s Guide 14.2.1.9 Interrupt Generation Logic .........................................................................14-4 14.2.1.10 Synchronizing Registers and Logic .........................................................14-5 14.2.2 UART Operation ..........................................................................................................14-5 14.2.2.1 Error Bits....................................................................................................14-6 14.2.2.2 Disabling the FIFOs ...................................................................................14-6 14.2.2.3 System/diagnostic Loopback Testing ........................................................14-6 14.2.2.4 UART Character Frame.............................................................................14-6 14.2.3 Interrupts .....................................................................................................................14-7 14.2.3.1 UARTMSINTR ...

Page 11

Chapter 17. IrDA .................................................................................................. 17-1 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 12

EP93xx User’s Guide Chapter 20. Real Time Clock With Software Trim ............................................ 20-1 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 13

Configuring the SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 14

... Figure 1-2. EP9302 Block Diagram ..............................................................................................................1-3 Figure 1-3. EP9307 Block Diagram ...............................................................................................................1-3 Figure 1-4. EP9312 Block Diagram ...............................................................................................................1-4 Figure 1-5. EP9315 Block Diagram ...............................................................................................................1-4 Figure 2-1. ARM920T Block Diagram ...........................................................................................................2-2 Figure 2-2. Typical AMBA AHB System ........................................................................................................2-7 Figure 2-3. Main Data Paths .........................................................................................................................2-8 xiv © ...

Page 15

Figure 4-1. Flow Chart of Boot ROM Software..............................................................................................4-4 Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices ...........................................................4-7 Figure 5-1. Phase Locked Loop (PLL) Structure ...........................................................................................5-4 Figure 5-2. Clock Generation System ...........................................................................................................5-6 Figure 5-3. Bus Clock Generation .................................................................................................................5-7 ...

Page 16

EP93xx User’s Guide Figure 10-4. Edge-triggered DREQ Mode .................................................................................................10-17 Figure 11-1. USB Focus Areas ...................................................................................................................11-2 Figure 11-2. Communication Channels .......................................................................................................11-3 Figure 11-3. Typical List Structure ..............................................................................................................11-4 Figure 11-4. Interrupt Endpoint Descriptor Structure ..................................................................................11-5 Figure 11-5. Sample Interrupt Endpoint Schedule ......................................................................................11-6 ...

Page 17

Figure 25-1. Different Types of Touch Screens ..........................................................................................25-2 Figure 25-2. 8-Wire Resistive Interface Switching Diagram .......................................................................25-5 Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram............................................................25-6 Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart ..................................................................25-9 Figure 25-5. 5-Wire Analog Resistive Interface ...

Page 18

EP93xx User’s Guide Table 3-6. LDC/STC Opcode Map ..............................................................................................................3-16 Table 3-7. CDP Opcode Map ......................................................................................................................3-16 Table 3-8. MCR Opcode Map .....................................................................................................................3-17 Table 3-9. MRC Opcode Map .....................................................................................................................3-17 Table 3-10. MaverickCrunch Instruction Set .............................................................................................3-18 Table 3-11. Mnemonic Codes for Loading Floating ...

Page 19

Table 8-2. bpp Memory Organization............................................................................................................8-5 Table 8-3. 4 bpp Memory Organization.........................................................................................................8-5 Table 8-4. 8 bpp Memory Organization.........................................................................................................8-6 Table 8-5. 16 bpp Memory Organization.......................................................................................................8-6 Table 8-6. 24 bpp Packed Memory Organization (4 pixel/ 3 words) .............................................................8-7 Table 8-7. 24 bpp Unpacked ...

Page 20

EP93xx User’s Guide Table 11-1. Frame Bandwidth Allocation ....................................................................................................11-7 Table 11-2. OpenHCI Register Addresses................................................................................................11-11 Table 12-1. PCMCIA Address Memory Ranges..........................................................................................12-5 Table 12-2. PCMCIA Pin Usage..................................................................................................................12-5 Table 12-3. Supported 8-Bit Accesses........................................................................................................12-8 Table 12-4. Supported 16-Bit Accesses......................................................................................................12-8 Table 12-5. PCMCIA Legacy Usage ...

Page 21

... Table 27-6. IDE Interface Register Map....................................................................................................27-10 Table 28-1. EP9301 and EP9302 GPIO Port to Pin Map............................................................................28-6 Table 28-2. EP9307 GPIO Port to Pin Map.................................................................................................28-6 Table 28-3. EP9312 GPIO Port to Pin Map.................................................................................................28-7 Table 28-4. EP9315 GPIO Port to Pin Map.................................................................................................28-8 DS785UM1 2 S Clock Generation................................................21-8 © ...

Page 22

EP93xx User’s Guide Table 28-5. GPIO Register Address Map....................................................................................................28-9 Table 29-1. Security Register List ...............................................................................................................29-2 Table 30-1. Glossary ...................................................................................................................................30-1 Table 31-1. EP93xx Register List................................................................................................................31-1 Revision History Revision Date September 14, UM1 2007 xxii Changes This is the Initial Release of ...

Page 23

... EP93xx processors. The EP9301, EP9302, EP9307, EP9312 processors are functional subsets of the EP9315 processor. All chapters in this Guide apply to the EP9315 processor. Most, but not all, chapters apply to the EP9301, EP9302, EP9307, EP9312 processors. maximum core frequency and the maximum high-speed bus frequency as well as number of package balls and package type for the EP93xx processors ...

Page 24

... AC’97 Controller 23: Synchronous Serial Port 24: Pulse Width Modulators 25: Analog Touch Screen Interface/ADC 26: Keypad Interface 27: IDE Interface 28: GPIO Interface 29: Security 30: Glossary P-2 Applicable EP93xx Processor EP9301 EP9302 5-ADC 5-ADC - - - - Copyright 2007 Cirrus Logic EP9307 EP9312 EP9315 8-Wire TS 8-Wire TS 8-Wire Devices 2 Devices X ...

Page 25

... EP9301 Data Sheet, Document Number - DS636PP5 2. EP9302 Data Sheet, Document Number - DS653PP3 3. EP9307 Data Sheet, Document Number - DS667PP4 4. EP9312 Data Sheet, Document Number - DS515PP7 5. EP9315 Data Sheet, Document Number - DS638PP1 P.3 Reference Documents ® 1. ARM 920T Technical Reference Manual, ARM Limited 2 ...

Page 26

Preface EP93xx User’s Guide • Registers are named using mixed upper and lower case alphanumeric, for example, SysCfg or PxDDR. Where there are multiple registers with the same names, a lower case “x” is used as a place holder. For ...

Page 27

REV: SBOOT: LCSn7, LCSn6: LASDO: LEEDA: LEECLK: LCSn1, LCSn2: DS785UM1 Revision, reads chip Version number Rev Rev Rev Rev D. Serial Boot Flag. This bit is read-only. 1 hardware ...

Page 28

Preface EP93xx User’s Guide P P-6 Copyright 2007 Cirrus Logic DS785UM1 ...

Page 29

... EP9301 EP9302 EP9307 EP9312 EP9315 Features of the EP93xx processors are summarized in in Figure 1-1 EP9301, Figure 1-2 Figure 1-5 EP9315. DS785UM1 Max High-Speed Bus Clock Rate 166 MHz 66 MHz 200 MHz 100 MHz 200 MHz 100 MHz 200 MHz 100 MHz ...

Page 30

... External Bus Bus EP9301 X - EP9302 X - EP9307 - X EP9312 - X EP9315 - X Note: “X” means that the function is included; “-” means that the function is not included. SDRAM SRAM, FLASH, ROM 12 Channel DMA 1/10/100 Ethernet MAC JTAG 2 USB 2.0 FS Host Boot ROM Vectored Inerrupts 1-2 Table 1-2 ...

Page 31

SDRAM SRAM, FLASH, ROM 12 Channel DMA 1/10/100 Ethernet MAC JTAG 2 USB 2.0 FS Host Boot ROM Vectored Inerrupts 2D Graphics 18-bit Raster LCD plus CCITT656 Video SDRAM SRAM, FLASH, ROM 12 Channel DMA 1/10/100 Ethernet MAC JTAG 3 ...

Page 32

... Coprocessor ARM920T I-Cache D-Cache Memory Management Unit High-Speed Bus (AHB) AHB/APB Bridge Peripheral Bus (APB) Figure 1-5. EP9315 Block Diagram Copyright 2007 Cirrus Logic UART1 with HDLC System Control – 2 PLLs 8-Wire Touchscreen ADC 8x8 Matrix Keypad 2 PWMs Enhanced GPIO, 2-wire, 2 LED ...

Page 33

Features of the EP93xx processors are: • ARM920T Core: • 200 MHz maximum run frequency and 100 MHz maximum high-speed bus frequency for EP9302, 9307, 9312, and 9315 only • 166 MHz maximum run frequency and 66 MHz maximum high-speed ...

Page 34

... I S interface with channels • 8x8 Matrix keypad scanner (in EP9307, EP9312, and EP9315 only) • PCMCIA Interface supporting 8-bit or 16-bit PCMCIA (PC Card) devices in EP9315 only • External Memory Options • 16-bit SDRAM interface ( banks) in EP9301 and 9302 only • 32-bit SDRAM interface ( banks) in EP9307, 9312, and 9315 only • ...

Page 35

... ARM920T’s compressed Thumb provides a space-efficient design that maximizes external instruction memory usage. ™ 1.4.2 MaverickCrunch The EP9302, EP9307, EP9312, and EP9315 processors include an advanced MaverickCrunch co-processor that provides mixed-mode math functions to greatly accelerate the floating-point processing capabilities of the ARM920T Core. The MaverickCrunch co- DS785UM1 ® ...

Page 36

... MaverickKey, please contact your Cirrus Logic sales representative. 1.4.4 Integrated Multi-Port USB 2.0 Full Speed Hosts with Transceivers The EP9307, EP9312, and EP9315 processors integrate three USB 2.0 Full Speed Host ports while the EP9301 and EP9302 integrate two of the ports. Fully compliant to the OHCI USB 2 ...

Page 37

... The enhanced GPIOs may individually be configured as inputs, outputs, or interrupt-enabled inputs. Nineteen enhanced GPIOs are in EP9301 and 9302 processors, 18 are in the EP9307 processor, and 16 are in EP9312 processor, and 24 are in the EP9315 processor. The standard GPIOs may individually be used as inputs, outputs, or (in some cases) open- drain pins ...

Page 38

... Touch-Screen Interface or General ADC Functionality The EP9301 and EP9302 processors include a 5-channel ADC. The EP9307, EP9212, and EP9315 processors include a 12-bit ADC, which can be utilized either as an 8-wire touch- screen interface or for general ADC functionality. The touch-screen interface performs all sampling, averaging, ADC range checking, and control for a wide variety of analog-resistive touch screens ...

Page 39

Core and Advanced High-Speed Bus (AHB) 2.1 Introduction This chapter describes the ARM920T Core and the Advanced High-Speed Bus (AHB). 2.2 Overview: ARM920T Core The ARM920T is a Harvard architecture core with separate 16 kbyte instruction and data caches ...

Page 40

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.2 Block Diagram 2 External Co-Proc Interface JTAG 2.2.3 Operations The ARM920T core follows a Harvard architecture and consists of an ARM9TDMI core, MMU, instruction and data cache. The core ...

Page 41

A 16 kbyte instruction and a 16 kbyte data cache are included to increase performance for cache-enabled memory regions. The 64-way associative cache also has lock-down capability. A 16-word Write Buffer allows cached instructions to be fetched and decoded while ...

Page 42

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.3.2 Memory Management Unit The MMU provides the translation and access permissions for the address and data ports for 2 the ARM9TDMI core. The MMU is controlled by page tables ...

Page 43

MMU Enable Enabling the MMU allows system memory control, but is also required if the Data Cache and the Write Buffer are to be used. Features are enabled for specific memory regions, as defined in the system page table. ...

Page 44

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.3.3.2 Data Cache Enable • A write to bit 2 of CP15 register 1 will enable or disable the Data Cache (D-Cache)/Write 2 Buffer • The D-Cache may only be ...

Page 45

Latched address and control • A simple Interface to on-chip peripherals such as UARTs and AC’97 rfa c e 2.2.6 AHB Implementation Details Peripherals or the ...

Page 46

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Ethernet 18 Bit Raster LCD I/F SDRAM Controller Memory/ PCMCIA Before an AMBA-to-AHB transfer can commence, the bus master must be granted access to the bus. ...

Page 47

A write data bus is used to move data from the master to a slave, while a read data bus is used to move data from a slave to the master. Every transfer consists of: • An address and control ...

Page 48

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.8.1 Main AHB Bus Arbiter This Main AHB Bus Arbiter controls bus master arbitration for the AHB bus. The AHB bus has 2 eight master interfaces: • ARM920T • DMA ...

Page 49

SDRAM Slave Arbiter The SDRAM Slave Arbiter prioritizes between accesses from the AHB bus and the Raster DMA bus access request from the AHB arrives at the same time as an access request from the Raster DMA, ...

Page 50

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.3.2 AHB-to-APB Bridge 2 The AHB-to-APB Bridge is an AHB slave that provides an interface between the high-speed AHB and the low-power APB. Read and write transfers on the AHB ...

Page 51

Note: Due to decoding optimization, the APB peripheral registers are aliased throughout each peripherals register bank. Do not attemp to access an unspecified register within the bank. 2.3.3 APB Slave An APB Slave responds to accesses initiated by bus masters. ...

Page 52

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 User System r10 r10 r11 r11 r12 r12 r13(sp) ...

Page 53

Saved Program Status Register contains CPSR after occurrence of an exception CP15 has 16 registers that control the core as described in Register DS785UM1 ARM920T Core and ...

Page 54

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 2.3.5 Memory Map The memory map for Synchronous Memory Boot and Asynchronous Memory Boot is shown in Table 2-7. If internal Boot Mode is selected and the register BootModeClr ...

Page 55

Note: The shaded memory areas are dedicated to system registers. Details of these registers are in Table 2-8. 2.3.6 Internal Register Map Table 2-8 on page 2-17 shows the memory map for internal registers. Registers are set to their default ...

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ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x8000_0140 - 0x8000_017C 0x8000_0180 - 0x8000_01FC 0x8000_0200 - 0x8000_023C 0x8000_0240 - 0x8000_027C 0x8000_0280 - 0x8000_02BC 0x8000_02C0 - 0x8000_02FC M2P Channel 6 Registers (Tx) 0x8000_0300 - 0x8000_033C 0x8000_0340 - ...

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Table 2-8. Internal Register Map (Continued) Address Register Name 0x8001_0090 RXDQBAdd 0x8001_0094 RXDQBLen 0x8001_0096 RXDQCurLen 0x8001_0098 RXDCurAdd 0x8001_009C RXDEnq 0x8001_00A0 RXStsQBAdd 0x8001_00A4 RXStsQBLen 0x8001_00A6 RXStsQCurLen 0x8001_00A8 RXStsQCurAdd 0x8001_00AC RXStsEnq 0x8001_00B0 TXDQBAdd 0x8001_00B4 TXDQBLen 0x8001_00B6 TXDQCurLen 0x8001_00B8 TXDQCurAdd 0x8001_00BC TXDEnq 0x8001_00C0 ...

Page 58

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x8002_0030 0x8002_0034 0x8002_0038 0x8002_003C 0x8002_0040 0x8002_0044 0x8002_0048 0x8002_004C 0x8002_0050 0x8002_0054 0x8002_0058 0x8002_005C 0x8002_0080 0x8002_0084 0x8003_xxxx 0x8003_0000 0x8003_0004 0x8003_0008 0x8003_000C 0x8003_0010 0x8003_0014 0x8003_0018 0x8003_001C 0x8003_0020 0x8003_0024 0x8003_0028 0x8003_002C 0x8003_0030 ...

Page 59

Table 2-8. Internal Register Map (Continued) Address Register Name 0x8003_006C CursorColor1 0x8003_0070 CursorColor2 0x8003_0074 CursorXYLoc 0x8003_0078 CursorDScanLHYLoc 0x8003_007C RasterSWLock 0x8003_0080 - 0x8003_00FC GrySclLUTR 0x8003_0200 VidSigRsltVal 0x8003_0204 VidSigCtrl 0x8003_0208 VSigStrtStop 0x8003_020C HSigStrtStop 0x8003_0210 SigClrStr 0x8003_0214 ACRate 0x8003_0218 LUTSwCtrl 0x8003_021C CursorBlinkColor1 0x8003_0220 ...

Page 60

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x8008_0008 0x8008_000C 0x8008_0010 - 0x8008_0014 0x8008_0018 0x8008_001C 0x8008_0020 0x8008_0024 0x8008_0028 0x8008_002C 0x8008_0030 0x8008_0034 0x8008_0038 0x8008_003C 0x8008_0040 0x8008_0044 - 0x8008_FFFC 0x8009_xxxx 0x8009_0000 0x8009_3FFF 0x800A_xxxx 0x800A_0000 0x800A_0004 0x800A_0008 0x800A_000C 0x800A_0010 ...

Page 61

Table 2-8. Internal Register Map (Continued) Address Register Name 0x800B_0008 VIC1RawIntr 0x800B_000C VIC1IntSelect 0x800B_0010 VIC1IntEnable 0x800B_0014 VIC1IntEnClear 0x800B_0018 VIC1SoftInt 0x800B_001C VIC1SoftIntClear 0x800B_0020 VIC1Protection 0x800B_0030 VIC1VectAddr 0x800B_0034 VIC1DefVectAddr 0x800B_0100 VIC1VectAddr0 0x800B_0104 VIC1VectAddr1 0x800B_0108 VIC1VectAddr2 0x800B_010C VIC1VectAddr3 0x800B_0110 VIC1VectAddr4 0x800B_0114 VIC1VectAddr5 0x800B_0118 ...

Page 62

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x800B_0FE8 0x800B_0FEC 0x800B_0FF0 - 0x800B_0FFC 0x800C_xxxx 0x800C_0000 0x800C_0004 0x800C_0008 0x800C_000C 0x800C_0010 0x800C_0014 0x800C_0018 0x800C_001C 0x800C_0020 0x800C_0030 0x800C_0034 0x800C_0100 0x800C_0104 0x800C_0108 0x800C_010C 0x800C_0110 0x800C_0114 0x800C_0118 0x800C_011C 0x800C_0120 0x800C_0124 0x800C_0128 ...

Page 63

Table 2-8. Internal Register Map (Continued) Address Register Name 0x800C_022C VIC2VectCntl11 0x800C_0230 VIC2VectCntl12 0x800C_0234 VIC2VectCntl13 0x800C_0238 VIC2VectCntl14 0x800C_023C VIC2VectCntl15 0x800C_0FE0 VIC2PeriphID0 0x800C_0FE4 VIC2PeriphID1 0x800C_0FE8 VIC2PeriphID2 0x800C_0FEC VIC2PeriphID3 0x800C_0FF0 - 0x800C_0FFC 0x8081_xxxx 0x8081_0000 Timer1Load 0x8081_0004 Timer1Value 0x8081_0008 Timer1Control 0x8081_000C Timer1Clear 0x8081_0020 ...

Page 64

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x8082_003C 0x8082_0040 0x8082_0044 0x8082_0048 0x8082_004C 0x8082_0050 0x8082_0054 0x8082_0058 0x8082_005C 0x8082_0060 0x8082_0064 0x8082_0068 0x8082_006C 0x8083_xxxx 0x8083_2714 Contact Cirrus Logic for details regarding implementation of device Security measures. 0x8084_xxxx 0x8084_0000 ...

Page 65

Table 2-8. Internal Register Map (Continued) Address Register Name 0x8084_005C IntStsF 0x8084_0060 RawIntStsF 0x8084_0064 GPIOFDB 0x8084_0068 - 0x8084_008C 0x8084_0090 GPIOAIntType1 0x8084_0094 GPIOAIntType2 0x8084_0098 GPIOAEOI 0x8084_009C GPIOAIntEn 0x8084_00A0 IntStsA 0x8084_00A4 RawIntStsA 0x8084_00A8 GPIOADB 0x8084_00AC GPIOBIntType1 0x8084_00B0 GPIOBIntType2 0x8084_00B4 GPIOBEOI 0x8084_00B8 GPIOBIntEn ...

Page 66

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x8088_0034 0x8088_0038 0x8088_003C 0x8088_0040 0x8088_0044 0x8088_0048 0x8088_004C 0x8088_0050 0x8088_0054 0x8088_0058 0x8088_005C 0x8088_0060 0x8088_0064 0x8088_0068 0x8088_006C 0x8088_0070 0x8088_0074 0x8088_0078 0x8088_007C 0x8088_0080 0x8088_0084 0x8088_0088 0x8088_008C 0x8088_0090 0x8088_0094 0x8088_0098 0x8088_009C 0x8088_00A0 ...

Page 67

Table 2-8. Internal Register Map (Continued) Address Register Name 0x808B_0008 IrAdrMatchVal 0x808B_000C IrFlag 0x808B_0010 IrData 0x808B_0014 IrDataTail 0x808B_0018 - 0x808B_001C 0x808B_0020 IrRIB 0x808B_0024 IrTR0 0x808B_0088 MIIR 0x808B_008C - 0x808B_018C 0x808C_xxxx 0x808C_0000 UART1Data 0x808C_0004 UART1RXSts 0x808C_0008 UART1LinCtrlHigh 0x808C_000C UART1LinCtrlMid 0x808C_0010 UART1LinCtrlLow ...

Page 68

ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x808E_xxxx 0x808E_0000 0x808E_0004 0x808E_0008 0x808E_000C 0x808E_0010 0x808E_0014 0x808E_0018 0x808E_001C 0x808E_0020 0x808E_0028 0x808E_0100 0x808E_0104 0x808E_0108 0x808E_0114 - 0x808E_0208 0x808E_020C 0x808E_0210 0x808E_0214 0x808E_0218 0x808E_021C 0x808F_xxxx 0x808F_0000 0x808F_0004 0x808F_0008 0x8090_xxxx 0x8090_0000 ...

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Table 2-8. Internal Register Map (Continued) Address Register Name 0x8091_000C PWM0Invert 0x8091_0010 PWM0Sync 0x8091_0020 PWM1_TC 0x8091_0024 PWM1_DC 0x8091_0028 PWM1_EN 0x8091_002C PWM1_INV 0x8091_0030 PWM1_SYNC 0x8092_xxxx 0x8092_0000 RTCData 0x8092_0004 RTCMatch 0x8092_0008 RTCSts 0x8092_000C RTCLoad 0x8092_0010 RTCCtrl 0x8092_0098 RTCSWComp 0x8093_xxxx 0x8093_0000 PwrSts 0x8093_0004 ...

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ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 Address 0x8095_0000 - 0x8FFF_FFFF 2-32 Table 2-8. Internal Register Map (Continued) Register Name Reserved Copyright 2007 Cirrus Logic Register Description DS785UM1 SW Lock ...

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... Introduction Note:This chapter applies only to the EP9302, EP9307, EP9312, and EP9315 processors. The MaverickCrunch co-processor accelerates IEEE-754 floating point arithmetic and 32-bit and 64-bit fixed point arithmetic operations. It provides an integer multiply-accumulate (MAC) that is considerably faster than the native MAC implementation in the ARM920T. The MaverickCrunch co-processor significantly accelerates the arithmetic processing required to encode/decode digital audio formats ...

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MaverickCrunch Co-Processor EP93xx User’s Guide • IEEE-754 single precision floating point (24-bit signed significand and 8-bit biased exponent) 3 • IEEE-754 double precision floating point (53-bit signed significand and 11-bit biased exponent) • 32-bit integer • 64-bit integer The co-processor ...

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Inexact Note that the division by zero exception is not supported as the MaverickCrunch co- processor does not provide division or square root. 3.1.3 Pipelines and Latency There are two primary pipelines within the MaverickCrunch co-processor. One handles all ...

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MaverickCrunch Co-Processor EP93xx User’s Guide A double precision value requires all 64 bits: Opcode 3 Sign A 32-bit integer is stored in the lower 32 bits of a 64-bit register and sign-extended when written, provided the UI bit in the ...

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With saturation enabled (the default), the maximum representable value is returned on overflow and the minimum representable value is returned on underflow. The maximum and minimum values depends on the operand size and whether the UI bit in the DSPSC ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 72 bits wide. If the accumulator saturation mode is disabled (the default), the accumulator bit fields are assigned as below for a 2’s complement integer. 3 Opcode 71 Sign If the saturation mode 1.63 is ...

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ARM instruction to gate the execution of that instruction based on the result of a Crunch compare operation. Table 3-3 illustrates the legal relationships and, for each one, the values written to the FCC ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 3.2 Programming Examples The examples below show two algorithms, each implemented using the standard 3 programming languages and the MaverickCrunch instruction set. 3.2.1 Example 1 Section 3.2.1.2, the same operation. Section 3.2.1.2 shows the program ...

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Example 2 The following function performs an FIR filter on the given input stream. The variable “data” points to an ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 3 mov 3.3 DSPSC Register DAID FWDEN Invalid Denorm Default: 0x0000_0000_0000_0000 Definition: MaverickCrunch Status and Control Register. Accessed ...

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DAID: HVID: ISAT: UI: INT: AEXC: DS785UM1 MaverickCrunch Architecture ID. This read-only value ...

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MaverickCrunch Co-Processor EP93xx User’s Guide SAT[1:0]: 3 FCC[1:0]: V: FWDEN: Invalid: Denorm: RM[1:0]: IXE: 3-12 Accumulator saturation mode select. These bits are set to select the saturation mode or to disable saturation for accumulator operations Saturation disabled for ...

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UFE: OFE: IOE: IX: UF: OF: IO: DS785UM1 Underflow Trap Enable. trapping for IEEE 754 underflow exceptions Disable software trapping for underflow exceptions 1 = Enable software trapping for underflow exceptions Overflow Trap Enable. Enables/disables software trapping for ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 3.4 ARM Co-Processor Instruction Format The ARM V4T architecture defines five ARM co-processor instructions: 3 • CDP - Co-processor Data Processing • LDC - Load Co-processor • STC - Store Co-processor • MCR - Move ...

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Table 3-5 shows the condition codes, which are bits [31:28] for each instruction format. Cond Mnemonic Meaning [31:28] Extension 0000 EQ Equal 0001 NE Not Equal 0010 CS/HS Carry Set/Unsigned Higher or Same 0011 CC/LO Carry Clear/Unsigned Lower 0100 MI ...

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MaverickCrunch Co-Processor EP93xx User’s Guide co-processor uses this bit to distinguish between single precision floating point/32-bit integer numbers (N=0) and double precision floating point/64-bit integer numbers (N=1). 3 • W: Specifies whether or not a calculated address is written back ...

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Instruction Set for the MaverickCrunch Co-Processor Table 3-10 summarizes ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Fields that are ignored by the co-processor are shaded. Dark shading implies that a field is processed by the ARM itself and can have any value, while light shading indicates that the 3 field, though ...

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Table 3-10. MaverickCrunch Instruction Set (Continued) Maverick ARM Crunch Co- Co- Processor Instruction Processor Instruction Instruction Type Type cfmv32al CRd, CRn cfmv32am CRd, CRn cfmv32ah CRd, CRn Moves from CDP accumulator cfmv32a CRd, CRn cfmv64a CRd, CRn Move to cfmvsc32 ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 3 Maverick ARM Crunch Co- Co- Processor Processor Instruction Instruction Type Type Comparisons MRC Floating point arithmetic, CDP single precision Floating point arithmetic, CDP double precision 32-bit integer CDP arithmetic 3-20 Table 3-10. MaverickCrunch Instruction ...

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Table 3-10. MaverickCrunch Instruction Set (Continued) Maverick ARM Crunch Co- Co- Processor Instruction Processor Instruction Instruction Type Type cfabs64 CRd, CRn cfneg64 CRd, CRn cfadd64 CRd, CRn, 64-bit integer CRm CDP arithmetic cfsub64 CRd, CRn, CRm cfmul64 CRd, CRn, CRm ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Bit Definitions Rn: CRd: Loading Integer Value from Memory 31:28 27:25 cond Description: Loads a 32- or 64-bit integer from memory into a MaverickCrunch register. Table 3-12. Mnemonic Codes for ...

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Mnemonic: Table 3-13. Mnemonic Codes for Storing Floating Point Values to Memory Mnemonic CFSTRS<cond> CRd, [Rn, <offset>]{!} CFSTRS<cond> CRd, [Rn], <offset> CFSTRD<cond> CRd, [Rn, <offset>]{!} CFSTRD<cond> CRd, [Rn], <offset> Bit Definitions: N: Rn: CRd: Store Integer Values to Memory 31:28 ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 3.5.2 Move Instructions Move Single Precision Floating Point from ARM to MaverickCrunch 3 31:28 27:24 cond Description: Moves a single precision floating point number from an ARM register into the upper ...

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Move Lower Half Double Precision Float from MaverickCrunch to ARM 31:28 27:24 23:22 cond Description: Moves the lower half of a double precision floating point value stored in a MaverickCrunch register into an ARM ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Move Lower Half 64-bit Integer from ARM to MaverickCrunch 31:28 27:24 3 cond Description: Moves the lower half of a 64-bit integer from an ARM register into the lower half of ...

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Move Upper Half 64-bit Integer from MaverickCrunch to ARM 31:28 27:24 23:22 cond Description: Moves the upper half of a 64-bit integer stored in a MaverickCrunch register into an ARM register. Mnemonic: CFMVR64H<cond> Rd, ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Move MaverickCrunch Register to Middle Accumulator 31:28 27:24 3 cond Description: Moves the low 32 bits of a MaverickCrunch register to the middle 32 bits of an accumulator (63:32). Mnemonic: CFMVAM32<cond> ...

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Move High Accumulator to MaverickCrunch Register 31:28 27:24 23:22 cond Description: Moves the highest 8 bits of an accumulator (71:64) to the lowest 8 bits of a MaverickCrunch register (7:0). Mnemonic: CFMV32AH<cond> CRd, CRn ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Move 64-bit Integer from Accumulator 31:28 27:24 3 cond Description: Saturates and rounds an accumulator value to 64 bits and moves the result to a MaverickCrunch register. Mnemonic: CFMV64A<cond> CRd, CRn ...

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Move from Control/Status Register to MaverickCrunch Register 31:28 27:24 23:22 cond Description: Moves a 64-bit value from the MaverickCrunch Status/Control register, DSPSC MaverickCrunch register. CRn is ignored. Mnemonic: CFMV32SC<cond> CRd, CRn Bit ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Convert Single Precision Floating Point to Double Precision Floating Point 31:28 27:24 3 cond Description: Converts a single precision floating point value to a double precision floating point value. Mnemonic: CFCVTSD<cond> ...

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Convert 32-bit Integer to Double Precision Floating Point 31:28 27:24 23:22 cond Description: Converts a 32-bit integer to a double precision floating point value. Mnemonic: CFCVT32D<cond> CRd, CRn Bit Definitions: CRd: CRn: Convert 64-bit ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Convert Single Precision Floating Point to 32-bit Integer 31:28 27:24 3 cond Description: Converts a single precision floating point number to a 32-bit integer. Mnemonic: CFCVTS32<cond> CRd, CRn Bit Definitions: CRd: ...

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Bit Definitions: CRd: CRn: 3.5.5 Shift Instructions Shift 32-bit Integer 31:28 27:24 23:22 cond Description: Shifts a 32-bit integer left or right. The shift count is a two’s complement integer stored in an ARM ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Shift 32-bit Integer Immediate 31:28 27:24 23:22 3 cond Definition: Shift a 32-bit integer by the count specified in the seven bit, two’s complement immediate value. A positive number indicates a ...

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Mnemonic: CFCMPS<cond> Rd, CRn, CRm Bit Definitions: CRn: CRm: Rd: Compare Double Precision Floating Point 31:28 27:24 23:22 cond Definition: Compares two double precision floating point numbers and stores an integer representing the result ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Rd: 3 Compare 64-bit Integers 31:28 27:24 cond Description: Compares two 64-bit integers and stores an integer representing the result in the ARM920T register; the highest four bits of the integer ...

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Bit Definitions: CRd: CRn: Single Precision Floating Point Negate 31:28 27:24 23:22 cond Description: Takes the negative of a single precision floating point number: CRd = -CRn Mnemonic: CFNEGS<cond> CRd, CRn Bit Definitions: CRd: ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Double Precision Floating Point Add 31:28 27:24 3 cond Description: Adds two double precision floating point numbers. Mnemonic: CFADDD<cond> CRd, CRn, CRm Bit Definitions: CRd: CRn: CRm: Single Precision Floating Point ...

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Single Precision Floating Point Multiply 31:28 27:24 23:22 cond Description: Multiplies two single precision floating point numbers: CRd = CRn Mnemonic: CFMULS<cond> CRd, CRn, CRm Bit Definitions: CRd: CRn: CRm: Double Precision Floating Point ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 64-bit Integer Absolute Value 31:28 27:24 3 cond Description: Computes the absolute value of a 64-bit integer. Mnemonic: CFABS64<cond> CRd, CRn Bit Definitions: CRd: CRn: 32-bit Integer Negate 31:28 27:24 cond ...

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Mnemonic: CFADD32<cond> CRd, CRn, CRm Bit Definitions: CRd: CRn: CRm: 64-bit Integer Add 31:28 27:24 23:22 cond Description: Adds two 64-bit integers. Mnemonic: CFADD64<cond> CRd, CRn, CRm Bit Definitions: CRd: CRn: CRm: 32-bit Integer ...

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MaverickCrunch Co-Processor EP93xx User’s Guide Bit Definitions: CRd: 3 CRn: CRm: 32-bit Integer Multiply 31:28 27:24 cond Description: Multiplies two 32-bit integers. Mnemonic: CFMUL32<cond> CRd, CRn, CRm Bit Definitions: CRd: CRn: CRm: 64-bit Integer Multiply 31:28 ...

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Bit Definitions: CRd: CRn: CRm: 32-bit Integer Multiply-Subtract 31:28 27:24 23:22 cond Description: Multiplies two 32-bit integers and subtracts the result from another 32-bit integer: CRd = CRd - (CRn Mnemonic: CFMSC32<cond> CRd, CRn, ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 32-bit Integer Multiply-Subtract, Result to Accumulator 31:28 27:24 3 cond Description: Multiplies two 32-bit integers, subtracts the product from a third 32-bit integer, and stores the result in an accumulator: Mnemonic: ...

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Integer Multiply-Subtract from Accumulator 31:28 27:24 23:22 cond Description: Multiplies two 32-bit integers, subtracts the product from an accumulator, and stores the result in an accumulator: CRa = CRd - (CRn Mnemonic: CFMSUBA32<cond> ...

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MaverickCrunch Co-Processor EP93xx User’s Guide 3 3-48 Copyright 2007 Cirrus Logic DS785UM1 ...

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Introduction The Boot ROM allows a program boot from the following devices: • SPI Flash • FLASH, SyncFLASH or SyncROM • UART1 4.1.1 Boot ROM Hardware Operational Overview The Boot ROM is an AHB slave device ...

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Boot ROM EP93xx User’s Guide Note that the code retrieved via UART1 and the SPI Serial Flash is not intended complete operating system image intended small ( kbyte) loader that ...

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not a Serial Download, attempt to read from SPI Serial Flash (see then follow Steps and D. A. Check if the first 4 bytes from the Serial Flash are equal to “CRUS” or ...

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Boot ROM EP93xx User’s Guide 4 4.2 Boot Options Table 4-1 shows configuration settings that are common to all boot modes. 4-4 Start Internal Boot Set Up Read Boot Clocks State Download UART Download ? Code Copy SPI Boot ? ...

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EECLK EEDAT BOOT1 Note: ASYNC boot mode is the preferred boot mode type for new designs. DS785UM1 Table 4-1. Boot Configuration Options ...

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Boot ROM EP93xx User’s Guide 4.2.1 UART Boot 4 Make sure that the boot configuration pins (see internal boot mode. EEDAT and BOOT0 should be pulled high and BOOT1 should be pulled low as shown in No flow control. The ...

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Code execution will start at address FLASH base + 0x0. The ARM Core will be in SVC mode. Note: CSn6 is the recommended chip select for Flash when performing an Internal boot. CSn0 must be connected to ...

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Boot ROM EP93xx User’s Guide 3. Run the internal boot code and boot from FLASH 4. Set the PLL back to use the external clock 4 5. Set up the SDRAM 6. Load the programs to SDRAM 7. Run from ...

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Introduction The System Controller (Syscon) provides: • Clock control • Power management • System configuration management These central resources are controlled by a set of software-locked registers, which can be used to prevent accidental accesses. Syscon generates the various ...

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System Controller EP93xx User’s Guide certain system variables such as RTC, SDRAM refresh control/global configuration, and the Syscon registers. 5 Note: If PLLs are enabled, user reset does NOT disable or reset the PLLs. They retain their frequency settings. • ...

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The normal boot function is described in Serial boot is functionally identical to normal boot except that the SBoot bit in the SysCfg register is set. This mode is available for a software configuration option that is readable by the ...

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System Controller EP93xx User’s Guide Note: ASYNC boot mode is the preferred boot mode type for new designs. 5 5.1.4 Software System Configuration Options There are several system configuration options selectable by the DeviceCfg and SysCfg registers. These registers provide ...

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Both PLLs are software programmable (each value is defined in “ClkSet2” on page 5-20 registers, respectively). The frequency of output clock Fout is determined by: Fout Here PLL1_X1FBD, PLL1_X2FBD, PLL1_X2IPD and PLL1_PS are the bit fields in the "ClkSet1" register. ...

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System Controller EP93xx User’s Guide 5 32 KHz Oscillator 14.7456 MHz Oscillator PLL1 CFG PLL2 CFG 5.1.5.2.1 Bus Clock Generation Figure 5-3 shows the generated clocks: the CPU clock (FCLK), the AHB bus clock (HCLK), and the APB bus clock ...

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External Clock HCLK Div MAX = 100 MHz PCLK Divide = There are some limitations of each clock. FCLK must be <=200 MHz, HCLK<=100 MHz and PCLK<=50 MHz and FCLK >= HCLK > PCLK. Refer to ...

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System Controller EP93xx User’s Guide Even though FCLK is the usual CPU clock, HCLK can optionally be used instead. Processor clocking modes are: 5 • Async mode • Sync mode • Fast Bus mode Both Async mode and Sync mode ...

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Steps for Clock Configuration The boot ROM must contain code that performs the following steps for a 14.7456 MHz crystal. The actual register values should be taken from the register descriptions for the desired clock setup. 1. After power ...

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System Controller EP93xx User’s Guide 5 Peripheral HCLK to the USB Hosts can be gated off as well to further save power. The USH_EN bit in the "PwrCnt" register serves the purpose. 5.1.6.2 System Power States The EP93xx has three ...

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Read Standby register & SHena = 1 Write to ClkSet1 register Standby Interrupt (if enabled) or return from ClkSet1 5.1.6.2.1 Power-on-Reset Run After power-on-reset, the ARM Core is automatically in run mode. 5.1.6.2.2 Run Standby Mode Once in run mode, ...

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System Controller EP93xx User’s Guide set. One example of this is when a power-on-reset is applied and this register bit is cleared. This means that this bit will not be set on boot-up and will have to be set to ...

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Registers This section contains the detailed register descriptions for registers in the Syscon block. Table 5-5 shows the address map for the registers in this block, followed by a detailed listing for each register. Address Name SW Locked 0x8093_0000 ...

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System Controller EP93xx User’s Guide Register Descriptions 5 PwrSts WDTFLG RSVD CLDFLG TEST_ RESET Address: 0x8093_0000 - Read Only Definition: The PwrSts system control register is the Power/State control register. Bit Descriptions: ...

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RSTFLG: TEST_RESET: CLDFLG: WDTFLG: CHIPID: CHIPMAN: PwrCnt FIR_EN RSVD UART USH_EN DMA BAUD M2M CH1 Address: 0x8093_0004 - Read / Write Definition: The PwrCnt system control register is the Clock/Debug ...

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System Controller EP93xx User’s Guide DMA M2M/P CHx: These bits enable the clocks to the DMA controller 5 USH_EN: UARTBAUD: FIR_EN: 5-16 channels. Note that a channels-enable bit MUST be asserted before any register within the DMA controller can be ...

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Standby and Halt Address: Standby - 0x8093_000C - Read Only Halt - 0x8093_0008 - Read Only Definition: The Standby and Halt registers allow entry into the power saving modes. A ...

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System Controller EP93xx User’s Guide STFClr Address: 0x8093_001C - Write Definition: Writing to the STFClr location will clear the CLDFLG, WDTFLG and RSTFLG in the register, the clearing. Bit Descriptions: RSVD: ...

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PLL1_X2FBD2: Note: The value in the register is the actual coefficient minus one. PLL1_X1FBD1: Note: The value in the register is the actual coefficient minus one. PLL1_PS: Note: This means that PLL1 FOUT is programmed to be 36,864,000 Hz on ...

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System Controller EP93xx User’s Guide nBYP1: 5 SMCROM: FCLKDIV: ClkSet2 USB DIV PLL2 X1FBD1 Address: 0x8093_0024 - Read/Write Definition: The ClkSet2 register is used for setting the dividers internally to PLL2 and ...

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PLL2_X2FBD2: Note: The value in the register is the actual coefficient minus one. PLL2_X1FBD1: Note: The value in the register is the actual coefficient minus one. PLL2_PS: Note: This means that PLL2 FOUT is programmed to be 48,000,000 Hz on ...

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System Controller EP93xx User’s Guide ScratchReg0, ScratchReg1 Address: ScratchReg0 - 0x8093_0040, Read/Write ScratchReg1 - 0x8093_0044, Read/Write Default: 0x0000_0000 Definition: Each of these locations provide a 32-bit read/write scratch register, that can ...

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BusMstrArb RSVD RSVD Address: 0x8093_0054 - Read/Write Definition: The Bus Master arbitration register (BusMstrArb) is used to configure the AHB master priority order. Bit Descriptions: RSVD: PRI_ORD: Priority Number 1 ...

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System Controller EP93xx User’s Guide DMA_ENFIQ: 5 USH_ENIRQ: USH_ENFIQ: MAC_ENIRQ: MAC_ENFIQ: BootModeClr Address: 0x8093_0058 - Write Only Definition: The BootModeClr register is a write-to-clear register. Reset activates the boot ROM remap function ...

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DeviceCfg SWRST D1onG D0onG IonU2 GonK HC3IN HC3EN HC1IN HC1EN HonIDE Address: 0x8093_0080 - Read/Write, Software locked Default: 0x0000_0000 Definition: Device Configuration Register. This register controls the operation of major ...

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System Controller EP93xx User’s Guide I2SonAC97 Note: The I S should be enabled on only one set of pins. Therefore I2SonAc97 and I2SonSSP are mutually exclusive. Setting both I2SonAc97 and I2SonSSP will cause unexpected behavior. I2SonSSP: 2 Note: ...

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HC3IN: HC3EN: HC1IN: HC1EN: TIN: U1EN: EXVC: U2EN: DS785UM1 0 - GPIO Port H used for IDE 1 - GPIO Port H used for GPIO HDLC3 clock in. This bit has no effect unless HC3EN pin ...

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System Controller EP93xx User’s Guide A1onG: 5 A2onG: CPENA: U3EN: MonG: TonG: GonK: IonU2: D0onG: D1onG: 5- Audio Port 1 on GPIO Port 1 pins are mapped to EGPIO. SDI1 is on ...

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SWRST: VidClkDiv VENA ESEL PSEL RSVD Address: 0x8093_0084 - Read/Write, Software locked Default: 0x0000_0000 Definition: Configures video clock for the raster engine. Selects input to VCLK dividers from either PLL1 ...

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System Controller EP93xx User’s Guide MIRClkDiv MENA ESEL PSEL Address: 0x8093_0088 - Read/Write, Software locked Default: 0x0000_0000 Definition: Configures MIR clock for the MIR IrDA. Selects input to MIR clock dividers ...

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I2SClkDiv SENA SLAVE ORIDE MENA ESEL PSEL RSVD Address: 0x8093_008C - Read/Write, Software locked Default: 0x0000_0000 Definition: Configures the I Bit Descriptions: RSVD: SENA: SLAVE: ORIDE: DROP: SPOL: LRDIV: DS785UM1 ...

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System Controller EP93xx User’s Guide SDIV: 5 MENA: ESEL: PSEL: PDIV: MDIV: KeyTchClkDiv TSEN KEN Address: 0x8093_0090 - Read/Write, Software locked Default: 0x0000_0000 Definition: Configures the Key Matrix, Touchscreen, and ADC clocks. ...

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ADIV: KEN: KDIV: CHIP_ID REV Address: 0x8093_0094 - Read Only Definition: Chip ID register. Bit Descriptions: RSVD: REV: 0: ID[15:0]: DS785UM1 ADC clock divider value ADC Clock is ...

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System Controller EP93xx User’s Guide SysCfg REV RSVD Address: 0x8093_009C - Read/Write, Software locked Default: 0x0000_0000 Definition: System Configuration Register. Provides various system configuration options. Bit Descriptions: RSVD: REV: SBOOT: LCSn7, ...

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LCSn1, LCSn2: SysSWLock RSVD Address: 0x8093_00C0 - Read/Write Default: 0x0000_0000 Definition: Syscon Software Lock Register. Provides software control port for all Syscon locked registers. Writing the LOCK field to 0xAA ...

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System Controller EP93xx User’s Guide 5 5-36 Copyright 2007 Cirrus Logic DS785UM1 ...

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Introduction The EP93xx processors contain two cascaded Vectored Interrupt Controllers (VIC). A Vectored Interrupt has improved latency compared with a simple interrupt controller, since it provides direct information about where the interrupt’s service routine is located and eliminates levels ...

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Vectored Interrupt Controller EP93xx User’s Guide 6 VICINTSOURCE[63:32] 2 VIC1 VICINTSOURCE[31:0] 1 VIC0 6.1.1 Interrupt Priority A FIQ interrupt has the highest priority (because the ARM9 core will always treat FIQ as higher priority), followed by vectored interrupt 0 to ...

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Any 16 of the 32 interrupts (per VIC) can be designated as ‘vectored’ by programming the Vector address registers, ‘VICxVectCntl0,’ on page An interrupt is designated as either IRQ or FIQ by programming the The IRQ and FIQ request logic ...

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Vectored Interrupt Controller EP93xx User’s Guide VIC Interrupt 6 Source ...

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TC1UI TC2UI AACINTR DMAM2P0 DMAM2P1 DMAM2P2 DMAM2P3 DMAM2P4 DMAM2P5 DMAM2P6 DMAM2P7 DMAM2P8 DMAM2P9 DMAM2M0 DMAM2M1 UART1RXINTR1 UART 1 Receive Interrupt. See DS785UM1 Timer Counter 1 Under Flow Interrupt. When Timer Counter 1 has underflowed (reached zero), this interrupt becomes active ...

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Vectored Interrupt Controller EP93xx User’s Guide UART1TXINTR1 6 UART1RXINTR2 UART 2 Receive Interrupt. See UART1TXINTR2 UART1RXINTR3 UART 3 Receive Interrupt. See UART1TXINTR3 INT_KEY INT_TOUCH INT_EXT[0] INT_EXT[1] INT_EXT[2] TINTR WEINT INT_RTC INT_IrDA INT_MAC INT_PROG 6-6 UART 1 Transmit Interrupt. See HDLC ...

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CLK1HZ V_SYNC INT_VIDEO_FIFO Video FIFO Interrupt. See INT_SSP1RX INT_SSP1TX TC3UI INT_UART1 SSPINTR INT_UART2 INT_UART3 USHINTR INT_PME DS785UM1 1 Hz clock interrupt. See Chapter With Software Trim". Vertical or Composite Sync/Frame Pulse Interrupt. See Chapter 7, "Raster Engine With Analog/LCD Integrated ...

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Vectored Interrupt Controller EP93xx User’s Guide INT_DSP GPIOINTR 6 I2SINTR 6.2 Registers The 2 VIC blocks have an identical register definition. The offset from the respective base address is the same: • VIC1 Base address: 0x800B_0000 • VIC2 Base Address: ...

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Address Type VIC base + 0208 Read /Write VIC base + 020C Read /Write VIC base + 0210 Read /Write VIC base + 0214 Read /Write VIC base + 0218 Read /Write VIC base + 021C Read /Write VIC base ...

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Vectored Interrupt Controller EP93xx User’s Guide Definition: IRQ Status Register. The VICxIRQStatus register provides the status of 6 interrupts after IRQ masking. Interrupts are in VIC1IRQStatus. Interrupts are in VIC2IRQStatus. Bit Descriptions: IRQStatus: VICxFIQStatus ...

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Definition: The VICxRawIntr register provides the status of the source interrupts (and software interrupts) to the interrupt controller. Bit Descriptions: RawIntr: VICxIntSelect Address: VIC1IntSelect: 0x800B_000C - Read/Write VIC2IntSelect: 0x800C_000C - ...

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Vectored Interrupt Controller EP93xx User’s Guide Definition: Interrupt Enable Register. The VICxIntEnable register enables the interrupt 6 requests by unmasking the interrupt sources. On reset, all interrupts are disabled (masked). Bit Descriptions: IntEnable: VICxIntEnClear ...

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Default: Don’t Care Definition: Software Interrupt Register. The VICxSoftInt register is used to generate software interrupts. Bit Descriptions: SoftInt: VICxSoftIntClear Address: VIC1SoftIntClear: 0x800B_001C - Write Only VIC2SoftIntClear: 0x800C_001C - Write ...

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Vectored Interrupt Controller EP93xx User’s Guide Definition: Protection Enable Register. The VICxProtection register enables or disables 6 protected register access. If the bus master cannot generate accurate protection information, leave this register in its reset state to allow User mode ...

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If you are not using the priority level in the VIC, write the VICxVectAddr register with any value (in order to disable the interrupt priority) at the beginning of your program not always clear when the ARM debuggers ...

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Vectored Interrupt Controller EP93xx User’s Guide VICxVectAddr7, 6 VICxVectAddr8, VICxVectAdd9, VICxVectAddr10, VICxVectAddr11, VICxVectAdd12, VICxVectAddr13, VICxVectAddr14, VICxVectAddr15 Address: VIC1VectAddr0: 0x800B_0100 - Read/Write VIC1VectAddr1: 0x800B_0104 - Read/Write VIC1VectAddr2: 0x800B_0108 - Read/Write VIC1VectAddr3: 0x800B_010C - ...

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VIC2VectAddr6: 0x800C_0118 - Read/Write VIC2VectAddr7: 0x800C_011C - Read/Write VIC2VectAddr8: 0x800C_0120 - Read/Write VIC2VectAddr9: 0x800C_0124 - Read/Write VIC2VectAddr10: 0x800C_0128 - Read/Write VIC2VectAddr11: 0x800C_012C - Read/Write VIC2VectAddr12: 0x800C_0130 - Read/Write VIC2VectAddr13: 0x800C_0134 - Read/Write VIC2VectAddr14: 0x800C_0138 - Read/Write VIC2VectAddr15: 0x800C_013C - Read/Write ...

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Vectored Interrupt Controller EP93xx User’s Guide VICxVectCntl15 Address: VIC1VectCntl0: 0x800B_0200 - Read/Write VIC1VectCntl1: 0x800B_0204 - Read/Write VIC1VectCntl2: 0x800B_0208 - Read/Write VIC1VectCntl3: 0x800B_020C - Read/Write VIC1VectCntl4: 0x800B_0210 - Read/Write VIC1VectCntl5: 0x800B_0214 - ...

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Note: Vectored interrupts are only generated if the interrupt is enabled. The specific interrupt is enabled in the VICxIntEnable register, and the interrupt is set to generate an IRQ interrupt in the VICxIntSelect register. This prevents multiple interrupts being generated ...

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Vectored Interrupt Controller EP93xx User’s Guide 6 6-20 Copyright 2007 Cirrus Logic DS785UM1 ...

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... Engine With Analog/LCD Integrated 7.1 Introduction Note: This chapter applies only to the EP9307, EP9312, and EP9315 processors. For additional information regarding the use EP93XX Raster Engine, see the application note, AN269, “Using the EP93xx’s Raster Engine” at: http://www.cirrus.com/en/pubs/appNote/AN269REV1.pdf. ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide The Raster engine also supports several hardware blinking modes, and 8-bit addressed lookup tables for grayscale or expanding color depth. The Raster also includes a video 7 stream signature ...

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Table 7-1. Raster Engine Video Mode Output Examples Display Horizontal Vertical x Type Resolution Resolution SXGA CRT 1280 x 1024 HDTV-2 LCD 1280 x 720 HDTV-2 CRT 1280 x 720 Since the frame buffer is stored in SDRAM memory, supporting ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide to one pixel combination blinking. For 16 bpp and 24 bpp modes, the LUT blink circuitry is usually bypassed and the blink functions are logic transformations of the pixel ...

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Frame Buffer organization. Table 7-2. Byte Oriented Frame Buffer Organization As stored in memory 4 bits per pixel 32-bit Word Byte 3 Byte 2 Byte1 bit 31 ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Table 7-2. Byte Oriented Frame Buffer Organization (Continued) As stored in memory 7 Pixel 3 Red Pixel 3 Green 32 bits per pixel (24 bits per pixel unpacked) 32-bit ...

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The Bright output signal can also be used for direct pulse width modulated CCFL brightness control that can be synchronized to the display frame rate. 7.3.7 Hardware Cursor The Raster Engine provides hardware cursor support. The cursor size ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 7 DAT(31:0) Video ADR(31:0) Image IN Line ADR Output CTR Scanner And Transfer Interface N_WR FULL HFULL N_CLR HADR(31:0) Cursor Address CNTRs HDAT(31:0) CREQ AMBA Cursor Cursor State Bus ...

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The load address counters at the beginning of the video frame. The VILOSATI continues to service the video ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide words on both the upper and lower half of the bus. The FIFO has an underflow interrupt indicator that can be used to determine if the system is providing ...

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A drawback to this mode is that it may cause problems with correctly viewing overlapping objects. Blink Brighter and Blink Dimmer modes shift the pixel data values by one bit ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide data into the unused LSBs of the bus to support the full color intensity range. This part of the multiplexing circuitry actually occurs before the blink logic stage. Once ...

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Shift Color Output P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) P(4) P(3) P(2) P(1) P(0) Mode Mode Mode single pixel 0x0 per clock up 0x0 0x4 R(1) R(0) ...

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Table 7-3. Output Pixel Transfer Modes (Continued) Shift Color Output P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) P(4) P(3) P(2) P(1) P(0) Mode Mode Mode ...

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Grayscale/Color Generator for Monochrome/Passive Low Color Displays The hardware raster engine has three built in matrix programmable grayscale generators. One generator is located on each of the red, green, and blue internal channels. These generators can be enabled to ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Assuming that pixel input value 0 is off, setting raster engine base + grayscale LUTx offset + 0x00, 0x20, 0x40, and 0x60 to all ‘0’s ensures that a 0 ...

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Grayscale Look-Up Table (GrySclLUT) Table 7-4. Grayscale Lookup Table (GrySclLUT) VCNT 11 11 (Lines) Frame Vert Horz Ctr Ctr Ctr HCNT 11 10 (Pixels) D18 D17 D16 base+ D18 D17 D16 base+84 D15 D14 D13 D12 D11 ...

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Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Where FRAME[1:0] = FRAME_CNT3 or FRAME_CNT4 as defined by FRAME at address Pixel_In, 7 VCNT[1:0] = VERT_CNT3 or VERT_CNT4 as defined by VERT at address Pixel_In, and HCNT[1:0] = ...

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