PC16550DN National Semiconductor, PC16550DN Datasheet

UART IC

PC16550DN

Manufacturer Part Number
PC16550DN
Description
UART IC
Manufacturer
National Semiconductor
Datasheet

Specifications of PC16550DN

Transceiver Type
RS232
Mounting Type
Through Hole
Peak Reflow Compatible (260 C)
No
Ic Function
UART IC
Supply Voltage
5V
No. Of Transceivers
1
Data Rate Max
128Kbps
Leaded Process Compatible
No
Supply Current
15mA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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C 1995 National Semiconductor Corporation
PC16550D Universal Asynchronous
Receiver Transmitter with FIFOs
General Description
The PC16550D is an improved version of the original 16450
Universal Asynchronous Receiver Transmitter (UART)
Functionally identical to the 16450 on powerup (CHARAC-
TER mode) the PC16550D can be put into an alternate
mode (FIFO mode) to relieve the CPU of excessive software
overhead
In this mode internal FIFOs are activated allowing 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) to be
stored in both receive and transmit modes All the logic is on
chip to minimize system overhead and maximize system ef-
ficiency Two pin functions have been changed to allow sig-
nalling of DMA transfers
The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM
and parallel-to-serial conversion on data characters re-
ceived from the CPU The CPU can read the complete
status of the UART at any time during the functional opera-
tion Status information reported includes the type and con-
dition of the transfer operations being performed by the
UART as well as any error conditions (parity overrun fram-
ing or break interrupt)
The UART includes a programmable baud rate generator
that is capable of dividing the timing reference clock input
by divisors of 1 to (2
driving the internal transmitter logic Provisions are also in-
cluded to use this 16
UART has complete MODEM-control capability and a proc-
essor-interrupt system Interrupts can be programmed to
the user’s requirements minimizing the computing required
to handle the communications link
The UART is fabricated using National Semiconductor’s ad-
vanced M
Basic Configuration
TRI-STATE is a registered trademark of National Semiconductor Corp
Can also be reset to 16450 Mode under software control
Note This part is patented
2
CMOS process
16
c
b
clock to drive the receiver logic The
1) and producing a 16
TL C 8652
c
clock for
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Capable of running all existing 16450 software
Pin for pin compatible with the existing 16450 except
for CSOUT (24) and NC (29) The former CSOUT and
NC pins are TXRDY and RXRDY respectively
After reset all registers are identical to the 16450 reg-
ister set
In the FIFO mode transmitter and receiver are each
buffered with 16 byte FIFO’s to reduce the number of
interrrupts presented to the CPU
Adds or deletes standard asynchronous communication
bits (start stop and parity) to or from the serial data
Holding and shift registers in the 16450 Mode eliminate
the need for precise synchronization between the CPU
and serial data
Independently controlled transmit receive line status
and data set interrupts
Programmable baud generator divides any input clock
by 1 to (2
Independent receiver clock input
MODEM control functions (CTS RTS DSR DTR RI
and DCD)
Fully programmable serial-interface characteristics
False start bit detection
Complete status reporting capabilities
TRI-STATE TTL drive for the data and control buses
Line break generation and detection
Internal diagnostic capabilities
Full prioritized interrupt system controls
5- 6- 7- or 8-bit characters
Even odd or no-parity bit generation and detection
1- 1 - or 2-stop bit generation
Baud generation (DC to 1 5M baud)
Loopback controls for communications link fault
isolation
Break parity overrun framing error simulation
16
b
1) and generates the 16
TL C 8652 – 1
RRD-B30M75 Printed in U S A
c
clock
June 1995

Related parts for PC16550DN

PC16550DN Summary of contents

Page 1

... M CMOS process Can also be reset to 16450 Mode under software control Note This part is patented Basic Configuration TRI-STATE is a registered trademark of National Semiconductor Corp C 1995 National Semiconductor Corporation TL C 8652 Features Capable of running all existing 16450 software Y Pin for pin compatible with the existing 16450 except ...

Page 2

ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS 4 0 TIMING WAVEFORMS 5 0 BLOCK DIAGRAM 6 0 PIN DESCRIPTIONS 7 0 CONNECTION DIAGRAMS 8 0 REGISTERS 8 1 Line Control Register 8 ...

Page 3

Absolute Maximum Ratings Temperature Under Bias Storage Temperature All Input or Output Voltages with Respect Power Dissipation Electrical Characteristics ...

Page 4

AC Electrical Characteristics Symbol Parameter t Address Strobe Width ADS t Address Hold Time Delay from Address AR t Address Setup Time Delay from Address AW t Chip Select Hold ...

Page 5

AC Electrical Characteristics Symbol Parameter Transmitter t Delay from WR WR (WR THR Reset Interrupt t Delay from RD RD (RD IIR) to Reset IR Interrupt (THRE) t Delay from Initial INTR Reset to Transmit IRS ...

Page 6

Timing Waveforms (Continued) Applicable Only When ADS is Tied Low Applicable Only When ADS is Tied Low Write Cycle Read Cycle 8652 – 8652 – 6 ...

Page 7

Timing Waveforms (Continued) Note 1 See Write Cycle Timing Note 2 See Read Cycle Timing Receiver Timing Transmitter Timing MODEM Control Timing 8652 – 8652 – 8652 – 9 ...

Page 8

Timing Waveforms (Continued) RCVR FIFO First Byte (This Sets RDR) RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set) Receiver Ready (Pin 29) FCR0 Note 1 This is the reading of the last byte in ...

Page 9

Timing Waveforms (Continued) Receiver Ready (Pin 29) FCR0 Note 1 This is the reading of the last byte in the FIFO Note 2 If FCR0 RCLKs e e SINT Transmitter Ready (Pin 24) FCR0 Transmitter ...

Page 10

Block Diagram Note Applicable pinout numbers are included within parenthesis 8652 – 16 ...

Page 11

Pin Descriptions The following describes the function of all UART pins Some of these descriptions reference internal circuits In the following descriptions a low represents a logic 0 (0V nominal) and a high represents a logic 1 ( ...

Page 12

... XIN to form a feedback circuit for the baud rate generator’s oscillator If the clock signal will be generated off-chip then this pin is unused 7 0 Connection Diagrams Dual-In-Line Package when the e Order Number PC16550DN See NS Package Number N40A the e 1 FCR3 0) and there are no charac when 8652 – ...

Page 13

Connection Diagrams TQFP Package Order Number PC16550DVEF See NS Package Number VEF44A Register Signal Interrupt Enable Register Interrupt Identification Register FIFO Control Line Control Register MODEM Control Register Line Status Register MODEM Status Register SOUT INTR (RCVR Errs) ...

Page 14

14 ...

Page 15

Registers The system programmer may access any of the UART reg- isters summarized in Table II via the CPU These registers control UART operations including transmission and recep- tion of data Each register bit in Table II has ...

Page 16

Registers (Continued) Bit 7 This bit is the Divisor Latch Access Bit (DLAB) It must be set high (logic 1) to access the Divisor Latches of the Baud Generator during a Read or Write operation It must be ...

Page 17

Registers (Continued) FIFO Interrupt Mode Identification Only Register Priority Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Type Level None Highest Receiver Line Status Second ...

Page 18

Registers (Continued) When the CPU accesses the IIR the UART freezes all inter- rupts and indicates the highest priority pending interrupt to the CPU While this CPU access is occurring the UART records new interrupts but does not ...

Page 19

Registers (Continued) Bit 7 This bit is the complement of the Data Carrier Detect (DCD) input If bit 4 of the MCR is set this bit is equivalent to OUT 2 in the MCR 8 ...

Page 20

Typical Applications (Continued) 20 ...

Page 21

... Physical Dimensions inches (millimeters) Plastic Dual-In-Line Package (N) Order Number PC16550DN NS Package Number N40A 44-Lead Plastic Chip Carrier (V) Order Number PC16550DV NS Package Number V44A 21 ...

Page 22

... National Semiconductor National Semiconductor National Semiconductores Japan Ltd Hong Kong Ltd Do Brazil Ltda Sumitomo Chemical 13th Floor Straight Block ...

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