PIC16F54T-I/SO Microchip Technology, PIC16F54T-I/SO Datasheet - Page 21

• Manufacturer Part Number: PIC16F54T-I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F54T-I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 12
• Program Memory Size: 768B (512 x 12)
• Program Memory Type: FLASH
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one, every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0> (Figure 3-6 and Figure 3-7).
For the PIC16F57 and PIC16F59, a page number must
be supplied as well. Bit 5 and bit 6 of the STATUS reg-
ister provide page information to bit 9 and bit 10 of the
PC (Figure 3-6 and Figure 3-7).
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 3-6 and Figure 3-7).
Instructions where the PCL is the destination or modify
PCL instructions, include MOVWF PCL, ADDWF PCL,
and BSF PCL,5.
For the PIC16F57 and PIC16F59, a page number
again must be supplied. Bit 5 and bit 6 of the STATUS
register provide page information to bit 9 and bit 10 of
the PC (Figure 3-6 and Figure 3-7).
FIGURE 3-6:
© 2007 Microchip Technology Inc.
GOTO Instruction
CALL or Modify PCL Instruction
Note:
Reset to '0'
Program Counter
PC
PC
Because PC<8> is cleared in the CALL
instruction or any modified PCL instruc-
tion, all subroutine calls or computed
jumps are limited to the first 256 locations
of any program memory page (512 words
long).
8
8
7
7
Instruction Word
Instruction Word
LOADING OF PC BRANCH
INSTRUCTIONS – PIC16F54
PCL
PCL
0
0
FIGURE 3-7:
3.5.1
If the PC is pointing to the last address of a selected
memory page, when it increments, it will cause the pro-
gram to continue in the next higher page. However, the
page preselect bits in the STATUS register will not be
updated. Therefore, the next GOTO, CALL or MODIFY
PCL instruction will send the program to the page
specified by the page preselect bits (PA0 or PA<1:0>).
For example, a NOP at location 1FFh (page 0)
increments the PC to 200h (page 1). A GOTO xxx at
200h will return the program to address xxh on page 0
(assuming that PA<1:0> are clear).
To prevent this, the page preselect bits must be
updated under program control.
3.5.2
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
Reset vector).
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is preselected.
Therefore, upon a Reset, a GOTO instruction at the
Reset vector location will automatically cause the
program to jump to page 0.
CALL or Modify PCL Instruction
GOTO Instruction
PC
PC
7
PAGING CONSIDERATIONS
PIC16F57 AND PIC16F59
EFFECTS OF RESET
7
10
2
10
2
9
Status
9
PA<1:0>
Status
PA<1:0>
Reset to ‘0’
8 7
8 7
LOADING OF PC BRANCH
INSTRUCTIONS – PIC16F57
AND PIC16F59
Instruction Word
Instruction Word
PIC16F5X
PCL
0
PCL
0
DS41213D-page 19
0
0