PIC18LF2410-I/ML Microchip Technology, PIC18LF2410-I/ML Datasheet

IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC

PIC18LF2410-I/ML

Manufacturer Part Number
PIC18LF2410-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2410-I/ML

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2410-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
The PIC18F2410/2510/4410/4510 Rev. B4 parts you
have received conform functionally to the Device Data
Sheet
described below. Any Data Sheet Clarification issues
related to the PIC18F2410/2510/4410/4510 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
The
PIC18F2410/2510/4410/4510 devices with these
Device/Revision IDs:
All of the issues listed here will be addressed in future
revisions of the PIC18F2410/2510/4410/4510 silicon.
1. Module: MSSP
TABLE 1:
© 2008 Microchip Technology Inc.
Param
70
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
No.
Part Number
PIC18F2410
PIC18F2510
PIC18F4410
PIC18F4510
In SPI Slave mode with slave select enabled
(SSPM<3:0> = 0100), the minimum time between
the falling edge of the SS pin and first SCK edge
is greater than specified in parameter 70 in
Table 25-16 and Table 25-17 of the above
referenced data sheet.
The updated specification is shown in bold in
Table 1.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
following
(DS39636C),
T
T
PIC18F2410/2510/4410/4510 Rev. B4 Silicon Errata
SS
SS
Symbol
L2
L2
3FFFFEh:3FFFFFh
SC
SC
EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)
H,
L
silicon
0001 0001 011
0001 0001 001
0001 0000 101
0001 0000 111
SS ↓ to SCK ↓ or SCK ↑ Input
Device ID
except
errata apply
for
in
the
PIC18F2410/2510/4410/4510
Revision ID
the
Characteristic
0 0111
0 0111
0 0111
0 0111
anomalies
only
device’s
to
2. Module: MSSP (SPI Mode)
FIGURE 1:
EXAMPLE 1:
LOOP BTFSS SSPSTAT, BF
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCK pulse may
occur on the first bit of the transmitted/received
data (Figure 1).
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit and then turn Timer2 back
on. Refer to Example 1 for sample code.
Date Codes that pertain to this issue:
All engineering and production devices.
SDO
SCK
BRA
MOVF
MOVWF RXDATA
MOVF
BCF
CLRF
MOVWF SSPBUF
BSF
Write SSPBUF
LOOP
SSPBUF, W
TXDATA, W
T2CON, TMR2ON
TMR2
T2CON, TMR2ON
3 T
Min
bit 0 = 1 bit 1 = 0
SCK PULSE VARIATION
USING TIMER2/2
AVOIDING THE INITIAL
SHORT SCK PULSE
CY
Max Units Conditions
;Data received?
;(Xmit complete?)
;No
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Timer2 off
;Clear Timer2
;Xmit New data
;Timer2 on
bit 2 = 1 . . . .
ns
DS80405A-page 1

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PIC18LF2410-I/ML Summary of contents

Page 1

... SS ↓ to SCK ↓ or SCK ↑ Input © 2008 Microchip Technology Inc. PIC18F2410/2510/4410/4510 2. Module: MSSP (SPI Mode) When the SPI is using Timer2/2 as the clock the anomalies source, a shorter than expected SCK pulse may occur on the first bit of the transmitted/received data (Figure 1). FIGURE 1: only to ...

Page 2

... None required. Date Codes that pertain to this issue: All engineering and production devices. and RXDTP R/W-0 R/W-0 TXCKP BRG16 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 R/W-0 — WUE ABDEN bit Bit is unknown © 2008 Microchip Technology Inc. ...

Page 3

... SSPBUF. If the WCOL is set, clear the bit in software and rewrite the SSPBUF register. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2410/2510/4410/4510 6. Module: Enhanced Capture/Compare/ PWM (ECCP) or With the ECCP configured for Half-Bridge PWM OSC mode (CCP1M< ...

Page 4

... Wait for the internal reference voltage (T to stabilize (typically 20 μs). 5. Re-enable BOR by setting (RCON<6> = 1). 6. Disable the HLVD by clearing HLVDEN (HLVDCON<4> = 0). Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. = For 11. Instead, use SBOREN ) IRVST SBOREN ...

Page 5

... Rev A Document (10/2008) Initial release of this document. Includes silicon issues 1 (MSSP), 2 (MSSP – SPI Mode), 3 (Enhanced Univer- sal Synchronous Receiver Transmitter – EUSART), 4 (10-Bit Analog-to-Digital Converter), 6 (Enhanced Capture/Compare/PWM – ECCP) and 7 (Resets – BOR). © 2008 Microchip Technology Inc. PIC18F2410/2510/4410/4510 5 (MSSP), DS80405A-page 5 ...

Page 6

... PIC18F2410/2510/4410/4510 NOTES: DS80405A-page 6 © 2008 Microchip Technology Inc. ...

Page 7

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 8

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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