PIC18LF2410-I/ML Microchip Technology, PIC18LF2410-I/ML Datasheet - Page 146

• Manufacturer Part Number: PIC18LF2410-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2410-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2X1X/4X1X
15.4.6
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally program-
mable dead-band delay is available to avoid shoot-
through current from destroying the bridge power
switches. The delay occurs at the signal transition from
the non-active state to the active state. See Figure 15-4
for illustration. Bits PDC6:PDC0 of the PWM1CON
register (Register 15-2) set the delay period in terms of
microcontroller instruction cycles (T
These bits are not available on 28-pin devices as the
standard CCP module does not support half-bridge
operation.
15.4.7
When the CCP1 is programmed for any of the Enhanced
PWM modes, the active output pins may be configured
for auto-shutdown. Auto-shutdown immediately places
the Enhanced PWM output pins into a defined shutdown
state when a shutdown event occurs.
REGISTER 15-2:
DS39636D-page 148
Note:
bit 7
bit 6-0
PROGRAMMABLE DEAD-BAND
DELAY
Programmable dead-band delay is not
implemented in 28-pin devices with
standard CCP modules.
ENHANCED PWM AUTO-SHUTDOWN
PWM1CON: PWM CONFIGURATION REGISTER
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
PDC6:PDC0: PWM Delay Count bits
Delay time, in number of F
a PWM signal to transition to active.
Legend:
R = Readable bit
-n = Value at POR
PRSEN
R/W-0
Note 1: Unimplemented on 28-pin devices and read as ‘0’.
goes away; the PWM restarts automatically
PDC6
R/W-0
CY
or 4 T
(1)
PDC5
OSC
R/W-0
OSC
W = Writable bit
‘1’ = Bit is set
).
/4 (4 * T
(1)
PDC4
(1)
R/W-0
OSC
A shutdown event can be caused by either of the
comparator modules, a low level on the Fault input pin
(FLT0) or any combination of these three sources. The
comparators may be used to monitor a voltage input
proportional to a current being monitored in the bridge
circuit. If the voltage exceeds a threshold, the
comparator switches state and triggers a shutdown.
Alternatively, a low digital signal on FLT0 can also trigger
a shutdown. The auto-shutdown feature can be disabled
by not selecting any auto-shutdown sources. The auto-
shutdown sources to be used are selected using the
ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS
register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
PSSBD1:PSSBD0 bits (ECCPAS3:ECCPAS0). Each
pin pair (P1A/P1C and P1B/P1D) may be set to drive
high, drive low or be tri-stated (not driving). The
ECCPASE bit (ECCPAS<7>) is also set to hold the
Enhanced PWM outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
) cycles, between the scheduled and actual time for
Note:
(1)
PDC3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
by
(1)
the
PDC2
R/W-0
© 2009 Microchip Technology Inc.
(1)
PSSAC1:PSSAC0
x = Bit is unknown
PDC1
R/W-0
(1)
PDC0
R/W-0
bit 0
(1)
and