PIC18LF2410-I/ML Microchip Technology, PIC18LF2410-I/ML Datasheet - Page 57

IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC

PIC18LF2410-I/ML

Manufacturer Part Number
PIC18LF2410-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2410-I/ML

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2410-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
5.2
5.2.1
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the instruc-
tion register during Q4. The instruction is decoded and
executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
FIGURE 5-3:
EXAMPLE 5-3:
© 2009 Microchip Technology Inc.
1. MOVLW 55h
2. MOVWF PORTB
3. BRA
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKO
(RC mode)
PIC18 Instruction Cycle
SUB_1
CLOCKING SCHEME
PORTA, BIT3 (Forced NOP)
OSC1
PC
Q1
Q2
Q3
Q4
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Execute INST (PC – 2)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
Q3
0
Q4
Execute 1
Fetch 2
T
CY
1
Q1
Fetch INST (PC + 2)
Execute INST (PC)
Q2
Execute 2
Fetch 3
PC + 2
T
CY
2
5.2.2
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the pipe-
lining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 5-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
PIC18F2X1X/4X1X
Q4
Execute 3
Fetch 4
T
CY
INSTRUCTION FLOW/PIPELINING
3
Q1
Execute INST (PC + 2)
Fetch INST (PC + 4)
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Q2
PC + 4
T
CY
4
Q3
Q4
DS39636D-page 59
T
CY
Internal
Phase
Clock
5

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