PIC18LF2410-I/ML Microchip Technology, PIC18LF2410-I/ML Datasheet - Page 66

• Manufacturer Part Number: PIC18LF2410-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2410-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2X1X/4X1X
TABLE 5-2:
DS39636D-page 68
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
BAUDCON
PWM1CON
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Bytes
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
VDIRMAG
ECCPASE
TMR0ON
ABDOVF
P1M1
PRSEN
CVREN
C2OUT
IDLEN
WCOL
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) (CONTINUED)
(2)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ACKSTAT
ECCPAS2
T3CCP2
P1M0
PDC6
CVROE
SSPOV
C1OUT
T08BIT
T1RUN
IRCF2
RCIDL
Bit 6
CKE
—
—
—
—
—
—
(2)
(2)
(1)
2
C Slave mode. SSP Baud Rate Reload Register in I
ECCPAS1
T1CKPS1
T3CKPS1
PDC5
SSPEN
ACKDT
VCFG1
ACQT2
DC1B1
DC2B1
IRCF1
IRVST
CVRR
C2INV
CHS3
T0CS
Bit 5
D/A
—
—
—
(2)
ECCPAS0
T1CKPS0
T3CKPS0
HLVDEN
PDC4
ACKEN
CVRSS
VCFG0
ACQT1
DC1B0
DC2B0
C1INV
IRCF0
SCKP
CHS2
T0SE
Bit 4
CKP
—
RI
P
(2)
T1OSCEN
CCP1M3
CCP2M3
PSSAC1
HLVDL3
T3CCP1
PDC3
SSPM3
PCFG3
ACQT0
BRG16
RCEN
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
TO
—
S
(2)
TMR2ON
CCP1M2
CCP2M2
T1SYNC
PSSAC0
T3SYNC
HLVDL2
PDC2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
Bit 2
CM2
R/W
PEN
PD
—
—
(2)
2
C Master mode.
‘
0
’
GO/DONE
PSSBD1
. Reset values are shown for 40/44-pin devices;
T2CKPS1
TMR1CS
TMR3CS
CCP1M1
CCP2M1
HLVDL1
PDC1
SSPM1
PCFG1
ADCS1
T0PS1
RSEN
CVR1
SCS1
WUE
Bit 1
POR
CM1
UA
—
(2)
(2)
© 2009 Microchip Technology Inc.
PSSBD0
SWDTEN
T2CKPS0
TMR1ON
TMR3ON
CCP1M0
CCP2M0
HLVDL0
PDC0
SSPM0
PCFG0
ADCS0
ABDEN
T0PS0
ADON
SCS0
CVR0
Bit 0
BOR
CM0
SEN
‘
BF
0
’
. See Section 2.6.4 “PLL in
(2)
(2)
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
0q-1 11q0 44, 50, 94
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
--- ---0
Value on
‘
0
’
. This bit is
on page:
52, 161,
52, 154,
52, 155,
53, 131,
Details
52, 117
52, 117
52, 115
52, 233
52, 249
52, 123
52, 123
52, 119
52, 126
52, 126
52, 125
52, 162
52, 165
53, 222
53, 222
53, 213
53, 214
53, 215
53, 132
53, 132
53, 132
53, 132
53, 131
53, 196
53, 148
53, 149
53, 229
53, 223
53, 129
53, 129
53, 127
32, 52
162
163
164
139