PIC18LF4221-I/ML Microchip Technology, PIC18LF4221-I/ML Datasheet

4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE

PIC18LF4221-I/ML

Manufacturer Part Number
PIC18LF4221-I/ML
Description
4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF4221-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F2221/2321/4221/4321
Family Data Sheet
Enhanced Flash Microcontrollers with
10-Bit A/D and nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39689F

Related parts for PIC18LF4221-I/ML

PIC18LF4221-I/ML Summary of contents

Page 1

... PIC18F2221/2321/4221/4321 Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc. Family Data Sheet DS39689F ...

Page 2

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... PIC18F4221 4K 2048 PIC18F4321 8K 4096 © 2009 Microchip Technology Inc. Peripheral Highlights (Continued): • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I Master and Slave modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit - Auto-Baud Detect • ...

Page 4

... Note 1: RB3 is the alternate pin for CCP2 multiplexing. DS39689F-page /RE3 REF REF / REF 2 20 REF PIC18F2221 4 18 PIC18F2321 RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA (1) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT © 2009 Microchip Technology Inc. ...

Page 5

... RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 (2) 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: For the QFN package recommended that the bottom pad be connected to V © 2009 Microchip Technology Inc. /RE3 REF 37 + REF ...

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... Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 Note 1: RB3 is the alternate pin for CCP2 multiplexing. DS39689F-page RC0/T1OSO/T13CKI 2 31 OSC2/CLKO/RA6 3 30 OSC1/CLKI/RA7 4 PIC18F4221 PIC18F4321 RE2/CS/AN7 27 7 RE1/WR/AN6 8 26 RE0/RD/AN5 9 25 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT 11 © 2009 Microchip Technology Inc. ...

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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 388 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 388 Index ................................................................................................................................................................................................. 389 The Microchip Web Site ..................................................................................................................................................................... 399 Customer Change Notification Service .............................................................................................................................................. 399 Customer Support .............................................................................................................................................................................. 399 Reader Response .............................................................................................................................................................................. 400 PIC18F2221/2321/4221/4321 Product Identification System ............................................................................................................ 401 © 2009 Microchip Technology Inc. DS39689F-page 7 ...

Page 8

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39689F-page 8 © 2009 Microchip Technology Inc. ...

Page 9

... PIC18F2221 • PIC18LF2221 • PIC18F2321 • PIC18LF2321 • PIC18F4221 • PIC18LF4221 • PIC18F4321 • PIC18LF4321 This family offers the advantages of all PIC18 micro- controllers – namely, high computational performance at an economical price – with the addition of high- endurance, Enhanced Flash program memory ...

Page 10

... Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2321), accommodate an operating V range of 4.2V to 5.5V. DD Low-voltage parts, designated by “LF” (such as PIC18LF2321), function over an extended V of 2.0V to 5.5V. © 2009 Microchip Technology Inc. Kbytes for Kbytes for range DD ...

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... Input Channels 10 Input Channels 13 Input Channels Resets (and Delays) RESET Instruction, Stack Underflow MCLR (optional), Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Packages © 2009 Microchip Technology Inc. PIC18F2221 PIC18F2321 DC – 40 MHz DC – 40 MHz 4096 8192 2048 4096 512 512 256 ...

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... PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT (3) OSC2/CLKO /RA6 (3) OSC1/CLKI /RA7 PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI (1) RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (2) MCLR/V /RE3 PP © 2009 Microchip Technology Inc. ...

Page 13

... RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 3.0 “Oscillator Configurations” for additional information. © 2009 Microchip Technology Inc. Data Bus<8> Data Latch 8 Data Memory (3 ...

Page 14

... In RC, EC and INTIO modes, OSC2 pin outputs CLKO which has one-fourth the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input O = Output Description P = Power © 2009 Microchip Technology Inc. ...

Page 15

... with I C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. ...

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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-circuit debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-circuit debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input O = Output Description P = Power © 2009 Microchip Technology Inc. ...

Page 17

... with I C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. ...

Page 18

... In RC, EC and INTIO modes, OSC2 pin outputs CLKO which has one-fourth the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input O = Output Description P = Power © 2009 Microchip Technology Inc. ...

Page 19

... with I C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. Pin Buffer Type Type PORTA is a bidirectional I/O port. 19 I/O TTL Digital I/O. ...

Page 20

... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-circuit debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-circuit debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input O = Output Description P = Power © 2009 Microchip Technology Inc. ...

Page 21

... with I C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. Pin Buffer Type Type PORTC is a bidirectional I/O port. 32 I/O ST Digital I/O. ...

Page 22

... Enhanced CCP1 output. 4 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. CMOS = CMOS compatible input or output I = Input O = Output Description P = Power © 2009 Microchip Technology Inc. ...

Page 23

... with I C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. Pin Buffer Type Type PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O. ...

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... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 24 © 2009 Microchip Technology Inc. ...

Page 25

... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS ( MCLR C1 ...

Page 26

... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXXX JP C1 and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...

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... The load capacitors should be placed next to the oscillator itself, on the same side of the board. © 2009 Microchip Technology Inc. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground ...

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... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 28 © 2009 Microchip Technology Inc. ...

Page 29

... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. © 2009 Microchip Technology Inc. FIGURE 3-1: (1) C1 (1) C2 Note 1: See Table 3-1 and Table 3-2 for initial values of C1 and C2 ...

Page 30

... Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) © 2009 Microchip Technology Inc. ...

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... EXT 20 pF ≤ C ≤ 300 pF EXT © 2009 Microchip Technology Inc. 3.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...

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... Locked Loop (PLL) in Internal Oscillator modes (see Figure 3-10). FIGURE 3-10: (OSCTUNE<6>) /4, OSC INTOSC CLKO OSC2 RA6 by writing to TUN<4:0> in the OSCTUNE register INTOSC AND PLL BLOCK DIAGRAM MHz PLLEN Phase F IN Comparator F OUT Loop Filter ÷4 VCO SYSCLK © 2009 Microchip Technology Inc. ...

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... Minimum frequency Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. 3.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift affect the controller operation in a variety of ways possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register ...

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... If the measured time is much greater than the calculated time, the internal oscillator block is running too fast. To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. © 2009 Microchip Technology Inc. ...

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... MHz (INTOSC) INTRC Source 31 kHz (INTRC) © 2009 Microchip Technology Inc. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. The PIC18F2221/2321/4221/4321 family of devices offers the Timer1 oscillator as a secondary oscillator ...

Page 36

... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 “Entering Power-Managed Modes”. © 2009 Microchip Technology Inc. ...

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... Secondary (Timer1) oscillator 00 = Primary oscillator Note 1: Reset state depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. (1) R/W-0 R/W-0 R R-0 IRCF1 IRCF0 ...

Page 38

... EC INTIO modes are used as the primary clock source. are listed in OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level (parameter 38, CSD OSC2 Pin © 2009 Microchip Technology Inc. ...

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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. 4.1.1 CLOCK SOURCES The SCS<1:0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...

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... Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. © 2009 Microchip Technology Inc. ...

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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2009 Microchip Technology Inc n-1 n ...

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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) T (1) OST T PLL 1 2 n-1 n Clock (2) Transition PC OSTS bit Set ; (approx). These intervals are not shown to scale. PLL . OSC © 2009 Microchip Technology Inc. ...

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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...

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... If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscil- lator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...

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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...

Page 46

... None LP, XT OST HSPLL T OST EC CSD (2) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc (1) (4) IOFS (3) ( OSTS rc (1) IOFS (3) ( OSTS rc (1) (4) IOFS © 2009 Microchip Technology Inc. ...

Page 47

... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 5-2 for time-out situations. © 2009 Microchip Technology Inc. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. ...

Page 48

... POR was set to ‘1’ by software immediately after Power-on Reset). DS39689F-page 48 (1) U-0 R/W-1 R-1 — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (2) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...

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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2009 Microchip Technology Inc. FIGURE 5- ...

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... BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. and operates as previously © 2009 Microchip Technology Inc. ...

Page 51

... Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. 5.5.3 PLL LOCK TIME-OUT With the PLL enabled in HSPLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...

Page 52

... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39689F-page 52 T PWRT T OST T PWRT T OST T PWRT T OST © 2009 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...

Page 53

... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2009 Microchip Technology Inc RISE > PWRT T OST T PWRT T OST T ...

Page 54

... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter POR BOR STKFUL 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ( © 2009 Microchip Technology Inc. STKPTR Register STKUNF ...

Page 55

... See Table 5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. MCLR Resets, Power-on Reset, WDT Reset, ...

Page 56

... Microchip Technology Inc. ...

Page 57

... See Table 5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. MCLR Resets, Power-on Reset, WDT Reset, ...

Page 58

... Microchip Technology Inc. ...

Page 59

... Reset Vector High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector On-Chip Program Memory Read ‘0’ © 2009 Microchip Technology Inc. 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...

Page 60

... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 can return these values to Stack Pointer STKPTR<4:0> 00010 © 2009 Microchip Technology Inc. ...

Page 61

... Note 1: Bit 7 and bit 6 are cleared by user software POR. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...

Page 62

... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. ...

Page 63

... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. 6.2.2 INSTRUCTION FLOW/PIPELINING An “ ...

Page 64

... REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2009 Microchip Technology Inc. ...

Page 65

... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2009 Microchip Technology Inc. 6.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...

Page 66

... General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...

Page 67

... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2009 Microchip Technology Inc. 7 Data Memory 1 ...

Page 68

... F90h — (2) F8Fh — (2) F8Eh — (3) F8Dh LATE (3) F8Ch LATD F8Bh LATC F8Ah LATB F89h LATA (2) F88h — (1) (2) F87h — (2) F86h — (2) F85h — F84h PORTE (3) F83h PORTD F82h PORTC F81h PORTB F80h PORTA © 2009 Microchip Technology Inc. ...

Page 69

... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 Top-of-Stack Upper Byte (TOS< ...

Page 70

... PDC1 PDC0 57, 162 0000 0000 (2) (2) PSSBD1 PSSBD0 57, 163 0000 0000 CVR1 CVR0 57, 249 0000 0000 CM1 CM0 57, 243 0000 0111 57, 143 xxxx xxxx xxxx xxxx 57, 143 TMR3CS TMR3ON 57, 141 0000 0000 © 2009 Microchip Technology Inc. ...

Page 71

... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 ...

Page 72

... The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 73

... Purpose Register File” location in the Access Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. © 2009 Microchip Technology Inc. The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 6.3.1 “ ...

Page 74

... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2009 Microchip Technology Inc. ...

Page 75

... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2009 Microchip Technology Inc. 6.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM ...

Page 76

... F00h Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...

Page 77

... F80h by using the BSR. FFFh © 2009 Microchip Technology Inc. Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. ...

Page 78

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 78 © 2009 Microchip Technology Inc. ...

Page 79

... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

Page 80

... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...

Page 81

... Initiates an EEPROM read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR © 2009 Microchip Technology Inc. U-0 R/W-0 R/W-x R/W-0 — FREE ...

Page 82

... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE ERASE TBLPTR<21:6> TABLE WRITE TBLPTR<21:3> TABLE READ – TBLPTR<21:0> TBLPTRL 0 © 2009 Microchip Technology Inc. ...

Page 83

... TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...

Page 84

... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...

Page 85

... CFGS bit to access program memory; • set WREN to enable byte writes. 8. Disable interrupts. © 2009 Microchip Technology Inc. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...

Page 86

... FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment ; TBLPTR ; loop until buffers are full © 2009 Microchip Technology Inc. ...

Page 87

... PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. ; disable interrupts ; required sequence ; write 55h ; write AAh ; start program (CPU stall) ; re-enable interrupts ; loop until done ...

Page 88

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 88 © 2009 Microchip Technology Inc. ...

Page 89

... EEPROM. © 2009 Microchip Technology Inc. The EECON1 register (Register 8-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...

Page 90

... Does not initiate an EEPROM read Legend Readable bit -n = Value at POR DS39689F-page 90 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...

Page 91

... BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...

Page 92

... Set for memory ; Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts © 2009 Microchip Technology Inc. ...

Page 93

... EEPGD CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — FREE WRERR WREN — ...

Page 94

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 94 © 2009 Microchip Technology Inc. ...

Page 95

... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 9-2: ...

Page 96

... WREG ; ADDWFC RES3 BTFSS ARG2H ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L SUBWF RES2 ; MOVF ARG1H SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L SUBWF RES2 ; MOVF ARG2H SUBWFB RES3 ; CONT_CODE : © 2009 Microchip Technology Inc ...

Page 97

... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ® ...

Page 98

... INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...

Page 99

... At least one of the RB<7:4> pins changed state (must be cleared in software None of the RB<7:4> pins have changed state Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...

Page 100

... This feature allows for software polling. DS39689F-page 100 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 101

... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. U-0 R/W-0 R/W-0 U-0 — ...

Page 102

... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...

Page 103

... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. U-0 R/W-0 R/W-0 R/W-0 — EEIF BCLIF HLVDIF W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 104

... R = Readable bit -n = Value at POR DS39689F-page 104 R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown ...

Page 105

... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. U-0 R/W-0 R/W-0 R/W-0 — EEIE BCLIE HLVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 106

... R = Readable bit -n = Value at POR DS39689F-page 106 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown ...

Page 107

... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. U-0 R/W-1 R/W-1 R/W-1 — EEIP BCLIP HLVDIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 108

... Section 5.1 “RCON Register”. (1) U-0 R/W-1 R-1 — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (2) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 109

... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2009 Microchip Technology Inc. 10.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...

Page 110

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 110 © 2009 Microchip Technology Inc. ...

Page 111

... High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. ...

Page 112

... System cycle clock output (F modes. O DIG LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. I ANA Main oscillator input connection. I ANA Main clock input connection. Description /4) in RC, INTIO1 and EC Oscillator OSC © 2009 Microchip Technology Inc. ...

Page 113

... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...

Page 114

... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the Configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0). bit, © 2009 Microchip Technology Inc. will end the CY ...

Page 115

... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2009 Microchip Technology Inc. I/O I/O Type O DIG LATB< ...

Page 116

... Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 55 — RBIP 55 INT2IF INT1IF 55 PCFG1 PCFG0 57 © 2009 Microchip Technology Inc. ...

Page 117

... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. © 2009 Microchip Technology Inc. Note Power-on Reset, these pins are configured as digital inputs. ...

Page 118

... LATC<7> data output PORTC<7> data input Asynchronous serial receive data input (EUSART module). O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Description © 2009 Microchip Technology Inc. ...

Page 119

... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Register © 2009 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset Bit 1 ...

Page 120

... EXAMPLE 11-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2009 Microchip Technology Inc. ...

Page 121

... P1D 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. I/O I/O Type O DIG LATD<0> data output. ...

Page 122

... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39689F-page 122 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 DC1B1 DC1B0 CCP1M3 CCP1M2 Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 58 CCP1M1 CCP1M0 57 © 2009 Microchip Technology Inc. ...

Page 123

... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2009 Microchip Technology Inc. The fourth pin of PORTE (MCLR/V /RE3 input PP only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...

Page 124

... R = Readable bit -n = Value at POR DS39689F-page 124 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 125

... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2009 Microchip Technology Inc. I/O I/O Type ...

Page 126

... Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2009 Microchip Technology Inc. ...

Page 127

... PSPIE ADIE (1) IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc Bit 5 Bit 4 ...

Page 128

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 128 © 2009 Microchip Technology Inc. ...

Page 129

... Prescale value Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...

Page 130

... Sync with Internal TMR0L Clocks Delay) OSC 3 ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...

Page 131

... Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...

Page 132

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 132 © 2009 Microchip Technology Inc. ...

Page 133

... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...

Page 134

... Special Event Trigger Synchronize 0 Detect Peripheral Clock Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Peripheral Clock Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...

Page 135

... PIC18FXXXX 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq C1 ( kHz 27 pF Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...

Page 136

... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2009 Microchip Technology Inc. ...

Page 137

... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...

Page 138

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 138 © 2009 Microchip Technology Inc. ...

Page 139

... T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS< ...

Page 140

... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 55 TMR2IF TMR1IF 58 TMR2IE TMR1IE 58 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...

Page 141

... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1) ...

Page 142

... Clear TMR3 TMR3L 8 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...

Page 143

... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...

Page 144

... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 144 © 2009 Microchip Technology Inc. ...

Page 145

... CCPx match (CCPxIF bit is set) 11xx = PWM mode Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. Note: Throughout this section and Section 17.0 “Enhanced Capture/Compare/PWM (ECCP) Module” ...

Page 146

... Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropri- ate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction © 2009 Microchip Technology Inc. ...

Page 147

... CCP1CON<3:0> Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2009 Microchip Technology Inc. 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...

Page 148

... Set CCP1IF Output Compare Logic Match 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...

Page 149

... The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”. 2: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...

Page 150

... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2009 Microchip Technology Inc. ...

Page 151

... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 17.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2009 Microchip Technology Inc. EQUATION 16-3: PWM Resolution (max) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared ...

Page 152

... CCP2M2 PSSAC1 PSSAC0 PSSBD1 (2) (2) (2) PDC5 PDC4 PDC3 PDC2 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 55 PD POR BOR 54 TMR2IF TMR1IF 58 TMR2IE TMR1IE 58 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 57 (2) (2) PSSBD0 57 (2) (2) (2) PDC1 PDC0 57 © 2009 Microchip Technology Inc. ...

Page 153

... PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. Enhanced features are discussed in detail in Section 17.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of the ECCP module are the same as described for the standard CCP module ...

Page 154

... PWM. and Timer RC2 RD5 All 40/44-pin devices: CCP1 RD5/PSP5 P1A P1B P1A P1B and Section 16.3 “Compare the processes described in “Setup for PWM RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2009 Microchip Technology Inc. ...

Page 155

... D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. 17.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation ...

Page 156

... The general relationship of the outputs in all configurations is summarized in Figure 17-2. 9.77 kHz 39.06 kHz FFh FFh OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...

Page 157

... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 17.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. 0 Duty Cycle Period (1) (1) Delay Delay 0 Duty ...

Page 158

... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...

Page 159

... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...

Page 160

... Reduce PWM for a PWM period before bits changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2009 Microchip Technology Inc. ...

Page 161

... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period ...

Page 162

... OSC OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared and PSSBD<1:0> bits R/W-0 R/W-0 R/W-0 (1) (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 163

... Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Unimplemented on 28-pin devices; bits read as ‘0’. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 ( Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 164

... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle ECCPASE Cleared by Firmware © 2009 Microchip Technology Inc. ...

Page 165

... Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. 17.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...

Page 166

... Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 55 PD POR BOR 54 TMR2IF TMR1IF 58 TMR2IE TMR1IE 58 TMR2IP TMR1IP 58 TMR3IF CCP2IF 58 TMR3IE CCP2IE 58 TMR3IP CCP2IP TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 57 (2) (2) PSSBD1 PSSBD0 57 (2) (2) (2) PDC2 PDC1 PDC0 57 © 2009 Microchip Technology Inc. ...

Page 167

... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2009 Microchip Technology Inc. 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four SPI modes are supported. To accomplish communication, typically three pins are used: • ...

Page 168

... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 169

... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented C™ mode only. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 ...

Page 170

... Note: To avoid lost data in Master mode, a read of the SSPBUF must be performed to clear the Buffer Full (BF) detect bit (SSPSTAT<0>) between each transmission. Note: The SSPBUF register cannot be used with read-modify-write instructions, such as BCF, BTFSC and COMF, etc. © 2009 Microchip Technology Inc. ...

Page 171

... Shift Register (SSPSR) MSb LSb PROCESSOR 1 © 2009 Microchip Technology Inc. Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 18.3.4 TYPICAL CONNECTION Figure 18-2 shows a typical connection between two microcontrollers ...

Page 172

... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...

Page 173

... SSPIF Interrupt Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...

Page 174

... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39689F-page 174 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 3 bit bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...

Page 175

... These bits are unimplemented on 28-pin devices and read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. 18.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...

Page 176

... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When the © 2009 Microchip Technology Inc. ...

Page 177

... SSPBUF is empty In Receive mode SSPBUF is full (does not include the ACK and Stop bits SSPBUF is empty (does not include the ACK and Stop bits) Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. 2 C™ MODE) R-0 R-0 R-0 CKE ...

Page 178

... CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C™ conditions were not valid for x = Bit is unknown © 2009 Microchip Technology Inc. ...

Page 179

... In Slave mode (7-Bit Addressing mode Address masking of ADD1 enabled 0 = Address masking of ADD1 disabled In Slave mode (10-Bit Addressing mode Address masking of ADD1 and ADD0 enabled 0 = Address masking of ADD1 and ADD0 disabled © 2009 Microchip Technology Inc. 2 C™ MODE) R/W-0 R/W-0 R/W-0 ...

Page 180

... W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 (1) (1) (1) / RSEN / SEN ADMSK1 bit 0 C module is active, these bits x = Bit is unknown R/W-0 R/W-0 ADD1 ADD0 bit Master x = Bit is unknown © 2009 Microchip Technology Inc. ...

Page 181

... I C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2009 Microchip Technology Inc. 18.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incom- ...

Page 182

... They only affect the lower address bits. Note 1: ADMSK<1> masks the Significant bits of the address. 2: The two Most Significant bits of the address are not affected by address masking. © 2009 Microchip Technology Inc. mask the two Least ...

Page 183

... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 18.4.4 “Clock Stretching” for more detail. © 2009 Microchip Technology Inc. 18.4.3.4 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...

Page 184

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) DS39689F-page 184 © 2009 Microchip Technology Inc. ...

Page 185

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 185 ...

Page 186

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) DS39689F-page 186 © 2009 Microchip Technology Inc. ...

Page 187

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-11: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK = 01001 (RECEPTION, 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 187 ...

Page 188

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-12: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) DS39689F-page 188 © 2009 Microchip Technology Inc. ...

Page 189

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 189 ...

Page 190

... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 18-13). © 2009 Microchip Technology Inc. ...

Page 191

... SDA DX SCL CKP WR SSPCON © 2009 Microchip Technology Inc. already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 18-14) ...

Page 192

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING) DS39689F-page 192 © 2009 Microchip Technology Inc. ...

Page 193

... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-16: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 193 ...

Page 194

... UA bit will not is enabled be set and the slave will begin receiving data after the Acknowledge (Figure 18-17). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ © 2009 Microchip Technology Inc. ...

Page 195

... Generate a Stop condition on SDA and SCL. FIGURE 18-18: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2009 Microchip Technology Inc. Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and ...

Page 196

... SSPCON2 register. 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2009 Microchip Technology Inc. ...

Page 197

... MHz 4 MHz 1 MHz 4 MHz 1 MHz © 2009 Microchip Technology Inc. Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 18-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD ...

Page 198

... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h © 2009 Microchip Technology Inc. ...

Page 199

... FIGURE 18-21: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2009 Microchip Technology Inc. Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the SCL line is sampled low before the SDA ...

Page 200

... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG 1st bit Write to SSPBUF occurs here T BRG Sr = Repeated Start T BRG © 2009 Microchip Technology Inc. ...

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