S29AL004D70TFI010 Spansion Inc., S29AL004D70TFI010 Datasheet - Page 13

• Manufacturer Part Number: S29AL004D70TFI010
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL004D70TFI010

• Memory Size: 4Mbit
• Memory Configuration: 512K X 8 / 256K X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Bus Operations
Legend:
L = Logic Low = V
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
February 18, 2005 S29AL004D_00_A1
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note 2)
Sector Unprotect (Note 2)
Temporary Sector Unprotect
“Sector Protection/Unprotection” section.
Word/Byte Configuration
Requirements for Reading Array Data
Operation
IL
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in
the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data
I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1)
address function.
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
control and gates array data to the output pins. WE# should remain at V
BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
, H = Logic High = V
IL
. CE# is the power control and selects the device. OE# is the output
A d v a n c e
V
0.3 V
CE# OE#
CC
Table 1. S29AL004D Device Bus Operations
X
X
L
L
L
L
L
IH
±
, V
Table 1
ID
H
X
H
X
H
H
X
L
= 12.0 ± 0.5 V, X = Don’t Care, A
WE
I n f o r m a t i o n
#
H
H
L
X
X
L
L
X
lists the device bus operations, the inputs and con-
RESET#
IH
V
0.3 V
S29AL004D
V
V
V
CC
), A17:A-1 in byte mode (BYTE# = V
H
H
H
L
ID
ID
ID
±
A6 = H, A1 = H,
A6 = L, A1 = H,
Sector Address,
Sector Address,
Addresses
(Note 1)
A0 = L
A0 = L
A
A
A
X
X
X
IN
IN
IN
IN
= Address In, D
High-Z
High-Z
High-Z
DQ0–
DQ7
D
D
D
D
D
OUT
IN
IN
IN
IN
BYTE#
High-Z
High-Z
High-Z
= V
D
D
D
IN
OUT
X
X
IL
IN
IN
IH
= Data In, D
).
IH
. The
DQ8–DQ14 = High-Z,
DQ8–DQ15
DQ15 = A-1
BYTE#
High-Z
High-Z
High-Z
High-Z
OUT
= V
X
X
= Data Out
IL
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