S29AL004D70TFI010 Spansion Inc., S29AL004D70TFI010 Datasheet - Page 20

• Manufacturer Part Number: S29AL004D70TFI010
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL004D70TFI010

• Memory Size: 4Mbit
• Memory Configuration: 512K X 8 / 256K X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Command Definitions
18
Hardware Data Protection
Reading Array Data
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to
for command definitions). In addition, the following hardware data protection
measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V
transitions, or from system noise.
Low V
When V
tects data during V
internal program/erase circuits are disabled, and the device resets. Subsequent
writes are ignored until V
proper signals to the control pins to prevent unintentional writes when V
greater than V
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
V
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
commands on the rising edge of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Writing specific address and data commands or sequences into the command
register initiates device operations.
command sequences. Writing incorrect address and data values or writing
them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase
Suspend mode. The system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming operation in the Erase Sus-
pend mode, the system may once again read array data with the same exception.
See
on this mode.
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
Erase Suspend/Erase Resume Commands‚ on page 22
CC
CC
is less than V
Write Inhibit
LKO
.
IL
CC
and OE# = V
power-up and power-down. The command register and all
LKO
CC
, the device does not accept any write cycles. This pro-
A d v a n c e
is greater than V
IH
S29AL004D
during power up, the device does not accept
Table on page 24
I n f o r m a t i o n
LKO
. The system must provide the
AC Characteristics‚ on page
CC
power-up and power-down
defines the valid register
IL
, CE# = V
for more information
Table on page 24
IH
or WE# =
S29AL004D_00_A1 February 18, 2005
CC
37.
is