STM32F101VFT6 STMicroelectronics, STM32F101VFT6 Datasheet - Page 16

MCU 32BIT 768KB FLASH 100LQFP

STM32F101VFT6

Manufacturer Part Number
STM32F101VFT6
Description
MCU 32BIT 768KB FLASH 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F101VFT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
STM32F101xF
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
80 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
112
Number Of Timers
15
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 105 C
Processor To Be Evaluated
STM32F101VF
Supply Current (max)
28 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-11113

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Description
2.3.5
2.3.6
2.3.7
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2.3.9
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Embedded SRAM
80 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F101xF and STM32F101xG access line family. It has
four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM,
PSRAM, NOR and NAND.
Functionality overview:
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.
Nested vectored interrupt controller (NVIC)
The STM32F101xF and STM32F101xG access line embeds a nested vectored interrupt
controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
The three FSMC interrupt lines are ORed in order to be connected to the NVIC
Write FIFO
Code execution from external memory except for NAND Flash and PC Card
The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at
36 MHz
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
Doc ID 17143 Rev 2
STM32F101xF, STM32F101xG

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