STM32F101RFT6 STMicroelectronics, STM32F101RFT6 Datasheet - Page 17

• Manufacturer Part Number: STM32F101RFT6
• Description: MCU 32BIT 768KB FLASH 64LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101RFT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: STM32F101xF
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 112
• Number Of Timers: 15
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: STM32F101RF
• Supply Current (max): 28 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-11111

STM32F101xF, STM32F101xG
2.3.10
2.3.11
2.3.12
2.3.13
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock is available when necessary (for example with failure
of an indirectly used external oscillator).
Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and
APB domains is 36 MHz. See
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
The bootloader is located in system memory. It is used to reprogram the Flash memory by
using USART1.
Power supply schemes
●
●
●
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
generated when V
than the V
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics
V
DD
POR/PDR
/V
Boot from user Flash: you have an option to boot from any of two memory banks. By
default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.
Boot from system memory
Boot from embedded SRAM
V
Provided externally through V
V
RCs and PLL (minimum voltage to be applied to V
used). V
V
registers (through power switch) when V
DD
SSA
BAT
DDA
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
PVD
and V
power supply and compares it to the V
DDA
DDA
threshold. The interrupt service routine can then generate a warning
PVD
= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
and V
DD
.
/V
DD
DDA
SSA
is below a specified threshold, V
drops below the V
must be connected to V
Doc ID 17143 Rev 2
Figure 2
DD
pins.
for details on the clock tree.
DD
PVD
is not present.
PVD
threshold and/or when V
DD
threshold. An interrupt can be
DDA
and V
Figure 9: Power supply
POR/PDR
is 2.4 V when the ADC or DAC is
SS
, respectively.
, without the need for an
for the values of
DD
/V
DDA
Description
scheme.
is higher
17/108