SPC5604PGF0MLL6 Freescale Semiconductor, SPC5604PGF0MLL6 Datasheet - Page 10

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SPC5604PGF0MLL6

Manufacturer Part Number
SPC5604PGF0MLL6
Description
IC MCU 32BIT 512KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MPC56xx Qorivvar
Datasheet

Specifications of SPC5604PGF0MLL6

Core Processor
e200z0h
Core Size
32-Bit
Speed
64MHz
Connectivity
CAN, FlexRay, LIN, SPI, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
64K x 8
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR has to be executed. It also provides a wide number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol (PCP) for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so
that all tasks which share the same resource can not preempt each other.
The INTC provides the following features:
1.5.7
The system status and configuration module (SSCM) provides central device functionality.
The SSCM includes these features:
1.5.8
The following list summarizes the system clock and clock generation on the MPC5604P:
1.5.9
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further, the FMPLL supports
programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all
software configurable.
The PLL has the following major features:
10
Unique 9-bit vector for each separate interrupt source
8 software triggerable interrupt sources
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Ability to modify the ISR or task priority: modifying the priority can be used to implement the Priority Ceiling Protocol
for accessing shared resources.
2 external high priority interrupts directly accessing the main core and I/O processor (IOP) critical interrupt mechanism
System configuration and status
— Memory sizes/status
— Device mode and security status
— Determine boot vector
— Search code flash for bootable sector
— DMA status
Debug status port enable and selection
Bus and peripheral abort enable/disable
Lock detect circuitry continuously monitors lock status
Loss of clock (LOC) detection for PLL outputs
Programmable output clock divider (1, 2, 4, 8)
FlexPWM module and eTimer module can run on an independent clock source
On-chip oscillator with automatic level control
Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by user application
Input clock frequency: 4–40 MHz
System status and configuration module (SSCM)
System clocks and clock generation
Frequency-modulated phase-locked loop (FMPLL)
MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor

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