SPC5604PGF0MLL6 Freescale Semiconductor, SPC5604PGF0MLL6 Datasheet - Page 12

• Manufacturer Part Number: SPC5604PGF0MLL6
• Description: IC MCU 32BIT 512KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MPC56xx Qorivvar

Specifications of SPC5604PGF0MLL6

• Core Processor: e200z0h
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CAN, FlexRay, LIN, SPI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 64K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.15
The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning.
The FCU module has the following features:
1.5.16
The MPC5604P SIUL controls MCU pad configuration, external interrupt, general purpose I/O (GPIO), and internal peripheral
multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and
discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
1.5.17
Different booting modes are available in the MPC5604P: booting from internal flash memory and booting via a serial link.
The default booting scheme uses the internal flash memory (an internal pull-down is used to select this mode). Optionally, the
user can boot via FlexCAN or LINFlex (using the boot assist module software).
A censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile memory.
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32-bit time-out register to set the time-out period
Programmable selection of system or oscillator clock for timer operation
Programmable selection of window mode or regular servicing
Programmable selection of reset or interrupt on an initial time-out
Master access protection
Hard and soft configuration lock bits
Reset configuration inputs allow timer to be enabled out of reset
FCU status register reporting the device status
Continuous monitoring of critical fault signals
User selection of critical signals from different fault sources inside the device
Critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device
and/or other circuitry (for example, safety relay or FlexRay transceiver)
Faults are latched into a register
Centralized general purpose input output (GPIO) control of as many as 80 input/output pins and 26 analog input-only
pads (package dependent)
All GPIO pins can be independently configured to support pull-up, pull down, or no pull
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
All peripheral pins (except ADC channels) can be alternatively configured as both general purpose input or output pins
ADC channels support alternative configuration as general purpose inputs
Direct readback of the pin value is supported on all pins through the SIUL
Configurable digital input filter that can be applied to some general purpose input pins for noise elimination: as many
as 4 internal functions can be multiplexed onto 1 pin
Fault collection unit (FCU)
System integration unit – Lite (SIUL)
Boot and censorship
MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor