SPC5604PGF0MLL6 Freescale Semiconductor, SPC5604PGF0MLL6 Datasheet - Page 19

• Manufacturer Part Number: SPC5604PGF0MLL6
• Description: IC MCU 32BIT 512KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MPC56xx Qorivvar

Specifications of SPC5604PGF0MLL6

• Core Processor: e200z0h
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CAN, FlexRay, LIN, SPI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 64K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.30
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:
1.5.31
The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format.
The JTAGC block is compliant with the IEEE standard.
The JTAG controller provides the following features:
1.5.32
The on-chip voltage regulator module provides the following features:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
— Watchpoint triggering, watchpoint triggers program tracing
Auxiliary Output Port
— 4 MDO (Message Data Out) pins
— MCKO (Message Clock Out) pin
— 2 MSEO (Message Start/End Out) pins
— EVTO (Event Out) pin
Auxiliary Input Port
— EVTI (Event In) pin
Support for CRC-16-CCITT (x25 protocol):
— x
Support for CRC-32 (Ethernet protocol):
— x
Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency
IEEE Test Access Port (TAP) interface with 4 pins (TDI, TMS, TCK, TDO)
Selectable modes of operation include JTAGC/debug or normal system operation.
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD
A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE
3 test data registers: a bypass register, a boundary scan register, and a device identification register.
A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry.
Uses external NPN (negative-positive-negative) transistor
Regulates external 3.3 V /5.0 V down to 1.2 V for the core logic
Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
Cyclic redundancy check (CRC)
IEEE 1149.1 JTAG controller
On-chip voltage regulator (VREG)
16
32
+ x
+ x
12
26
+ x
+ x
5
23
+ 1
+ x
22
+ x
16
MPC5604P Microcontroller Data Sheet, Rev. 7
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1
19