SPC5604PGF0MLL6 Freescale Semiconductor, SPC5604PGF0MLL6 Datasheet - Page 6

• Manufacturer Part Number: SPC5604PGF0MLL6
• Description: IC MCU 32BIT 512KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MPC56xx Qorivvar

Specifications of SPC5604PGF0MLL6

• Core Processor: e200z0h
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CAN, FlexRay, LIN, SPI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 64K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
Clock generation module
(MC_CGM)
Controller area network (FlexCAN) Supports the standard CAN communications protocol
Cross triggering unit (CTU)
Crossbar switch (XBAR)
Cyclic redundancy check (CRC)
Deserial serial peripheral interface
(DSPI)
Enhanced direct memory access
(eDMA)
Enhanced timer (eTimer)
Error correction status module
(ECSM)
External oscillator (XOSC)
Fault collection unit (FCU)
Flash memory
Frequency-modulated
phase-locked loop (FMPLL)
Interrupt controller (INTC)
JTAG controller
LINFlex controller
Mode entry module (MC_ME)
Periodic interrupt timer (PIT)
Peripheral bridge (PBRIDGE)
Power control unit (MC_PCU)
Block
Table 2. MPC5604P series block summary
MPC5604P Microcontroller Data Sheet, Rev. 7
Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Provides logic and control required for the generation of system and peripheral
clocks
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width
CRC checksum generator
Provides a synchronous serial interface for communication with external devices
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels
Provides enhanced programmable up/down modulo counting
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Provides functional safety to the device
Provides non-volatile storage for program code, constants and variables
Generates high-speed system clocks and supports programmable frequency
modulation
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with minimum load on CPU
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Produces periodic interrupts and triggers
Interface between the system bus and on-chip peripherals
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Function
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