SPC5604PEF0MLQ6 Freescale Semiconductor, SPC5604PEF0MLQ6 Datasheet - Page 18

• Manufacturer Part Number: SPC5604PEF0MLQ6
• Description: IC MCU 32BIT 512KB FLASH 144LQFP
• Manufacturer: Freescale Semiconductor
• Series: MPC56xx Qorivvar

Specifications of SPC5604PEF0MLQ6

• Core Processor: e200z0h
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CAN, FlexRay, LIN, SPI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 108
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 64K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.28
The cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU
load during the PWM period and with minimized CPU load for dynamic configuration.
It implements the following features:
1.5.29
The NDI (Nexus Development Interface) block provides real-time development support capabilities for the MPC5604P Power
Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for
MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several
individual Nexus blocks that are selected to provide the development support interface for this device. The NDI block interfaces
to the host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard.
The development support provided includes access to the MCU’s internal memory map and access to the processor’s internal
registers during run time.
The Nexus Interface provides the following features:
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— ADC state machine managing 3 request flows: regular command, hardware injected command, software injected
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
CTU control mode features
— Triggered mode only
— 4 independent result queues (2 × 16 entries, 2 × 4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit part
— DMA compatible interfaces
Double buffered trigger generation unit with as many as eight independent triggers generated from external triggers
Trigger generation unit configurable in sequential mode or in triggered mode
Each Trigger can be appropriately delayed to compensate the delay of external low pass filter
Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger has the capability to generate consecutive commands
ADC conversion command allows to control ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
Configured via the IEEE 1149.1
All Nexus port pins operate at V
Nexus 2+ features supported
— Static debug
— Watchpoint messaging
— Ownership trace messaging
— Program trace messaging
— Real time read/write of any internally memory mapped resources through JTAG pins
— Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of
command
information
Cross triggering unit (CTU)
Nexus development interface (NDI)
MPC5604P Microcontroller Data Sheet, Rev. 7
DDIO
(no dedicated power supply)
Freescale Semiconductor