SPC5604PEF0MLQ6 Freescale Semiconductor, SPC5604PEF0MLQ6 Datasheet - Page 9

• Manufacturer Part Number: SPC5604PEF0MLQ6
• Description: IC MCU 32BIT 512KB FLASH 144LQFP
• Manufacturer: Freescale Semiconductor
• Series: MPC56xx Qorivvar

Specifications of SPC5604PEF0MLQ6

• Core Processor: e200z0h
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CAN, FlexRay, LIN, SPI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 108
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 64K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

array controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit wide prefetch buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory
array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states.
The flash memory module provides the following features:
1.5.5
The MPC5604P SRAM module provides up to 40 KB of general-purpose memory.
ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family devices with an
e200z6 core and 64-bit wide ECC.
The SRAM module provides the following features:
1.5.6
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems. The INTC handles 147 selectable-priority interrupt sources.
Freescale Semiconductor
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As much as 576 KB flash memory
— 8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash
— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash
— Full Read While Write (RWW) capability between code and data flash
Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to
prefetch code or data or both)
Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page buffer miss at 64 MHz
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
Hardware and software configurable read and write access protections on a per-master basis
Configurable access timing allowing use in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for
emulation of other memory types.
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page sizes
— Code flash memory: 128 bits (4 words)
— Data flash memory: 32 bits (1 word)
ECC with single-bit correction, double-bit detection for data integrity
— Code flash memory: 64-bit ECC
— Data flash memory: 32-bit ECC
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Censorship protection scheme to prevent flash memory content visibility
Hardware support for EEPROM emulation
Supports read/write accesses mapped to the SRAM from any master
Up to 40 KB general purpose SRAM
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back
with a read to same memory block
Static random access memory (SRAM)
Interrupt controller (INTC)
MPC5604P Microcontroller Data Sheet, Rev. 7
9