QLX4600SIQSR Intersil, QLX4600SIQSR Datasheet - Page 7

• Manufacturer Part Number: QLX4600SIQSR
• Description: IC EQUALIZER REC 6.25GBPS 46QFN
• Manufacturer: Intersil

Specifications of QLX4600SIQSR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
NOTES:
10. During line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the
11. The data pattern preceding line silence mode is comprised of the PCIe electrical idle ordered set (EIOS). The data pattern
12. The data pattern preceding or following line silence mode is comprised of the SAS-2 ALIGN (0) sequence for OOB signaling at
Serial Bus Timing Characteristics
Line Silence-to-Data
Response Time
Timing Difference (SAS)
3. After channel loss, differential amplitudes at QLx4600-S30 inputs must meet the input voltage range specified in “Absolute
4. Temperature = +25°C, V
5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
6. Measured using a PRBS 2
7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
8. For active data mode, cable input amplitude is 400mV
9. Measured differentially across the data source.
CLK Setup Time
DI Setup Time
DI Hold Time
ENB ‘HIGH’
Boost Setting Operational
DO Hold Time
Clock Rate
Maximum Ratings” on page 5.
signal (as measured at the input to the channel). Total jitter (TJ) is DJ
media-induced loss only.
is 20mV
QLx4600 that are greater than 20mV
following line silence mode is comprised of the PCIe electrical idle exit sequence (EIES).
3Gb/s, and amplitude of 800mV
PARAMETERS
PARAMETER
P-P
(differential) or less.
DD
|t
7
SYMBOL
7
SYMBOL
-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
DS
t
t
t
t
f
= 1.2V.
t
HEN
SCK
CLK
SDI
HDI
t
t
CQ
SD
D
- t
Typical values are at V
V
P-P
SD
DD
.
|
= 1.1V to 1.3V, T
From the falling edge of ENB
Prior to the rising edge of CLK
From the rising edge of CLK
From the falling edge of the last data bit’s CLK
From ENB ‘HIGH’
From the rising edge of CLK to DO transition
Reference clock for serial bus EQ programming
P-P
Time to transition from line silence mode
(muted output) to active data on 20m
24AWG standard twin-axial cable at 5Gb/s
Time from first bit of ALIGN(0) for SAS
OOB signaling to 450mV
Meritec 24AWG 20m; 3Gb/s
For SAS OOB signaling support; Meritec
24AWG 20m
.
QLx4600-S30
CONDITION
P-P
A
DD
= 0°C to +70°C. (Continued)
(differential) or greater. For line silence mode, cable input amplitude
CONDITION
= 1.2V, T
P-P
A
output;
= +25°C, and V
PP
+ 14.1 x RJ
MIN
IN
RMS
= 800mV
.
TYP
MIN
10
10
10
12
6
P-P
, unless otherwise noted.
MAX
TYP
20
19
5
UNITS NOTES
MAX
November 19, 2009
10
20
ns
ns
ns
UNITS
FN6979.1
MHz
8, 11
ns
ns
ns
ns
ns
ns
12
12