SM72485X/NOPB National Semiconductor, SM72485X/NOPB Datasheet - Page 10

• Manufacturer Part Number: SM72485X/NOPB
• Description: IC BUCK SWITCH 100V REG 8-LLP
• Manufacturer: National Semiconductor
• Series: SolarMagic™r
• Type: Step-Down (Buck)r

Specifications of SM72485X/NOPB

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: Adj to 2.5V
• Current - Output: 150mA
• Frequency - Switching: 50kHz ~ 1.1MHz
• Voltage - Input: 6 V ~ 95 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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rent without saturating or exceeding its temperature rating, it
also must be capable of carrying the maximum guaranteed
value of the SM72485’s current limit threshold (360 mA) with-
out saturating, since the current limit is reached during start-
up.
The DC resistance of the inductor should be as low as pos-
sible to minimize its power loss.
C3: The capacitor on the V
filtering and stability, but its primary purpose is to prevent false
triggering of the V
tions. C3 should be no smaller than 0.47 µF.
C2, and R3: When selecting the output filter capacitor C2, the
items to consider are ripple voltage due to its ESR, ripple
voltage due to its capacitance, and the nature of the load.
ESR and R3: A low ESR for C2 is generally desirable so as
to minimize power losses and heating within the capacitor.
However, the regulator requires a minimum amount of ripple
voltage at the feedback input for proper loop operation. For
the SM72485 the minimum ripple required at pin 5 is 25 mV
p-p, requiring a minimum ripple at V
minimum ripple current (at minimum Vin) is 32 mA p-p, the
minimum ESR required at V
Since quality capacitors for SMPS applications have an ESR
considerably less than this, R3 is inserted as shown in the
Block Diagram. R3’s value, along with C2’s ESR, must result
in at least 25 mV p-p ripple at pin 5. Generally, R3 will be 0.5
to 4.0Ω.
R
by this resistor must be greater than the maximum normal off-
time, which occurs at maximum input voltage. Using Equation
2, the minimum on-time is 476 ns, yielding an off-time of 3.8
µs (at 234 kHz). Due to the 25% tolerance on the on-time, the
off-time tolerance is also 25%, yielding a maximum off-time
of 4.75 µs. Allowing for the response time of the current limit
detection circuit (350 ns) increases the maximum off-time to
5.1 µs. This is increased an additional 25% to 6.4 µs to allow
for the tolerances of Equation 3. Using Equation 3, R
culates to 310 kΩ at V
resistor will be used.
D1: The important parameters are reverse recovery time and
forward voltage. The reverse recovery time determines how
long the reverse current surge lasts each time the buck switch
is turned on. The forward voltage drop is significant in the
event the output is short-circuited as it is only this diode’s
voltage which forces the inductor current to reduce during the
forced off-time. For this reason, a higher voltage is better, al-
though that affects efficiency. A good choice is a Schottky
power diode, such as the DFLS1100. D1’s reverse voltage
rating must be at least as great as the maximum Vin, and its
current rating be greater than the maximum current limit
threshold (360 mA).
C1: This capacitor’s purpose is to supply most of the switch
current during the on-time, and limit the voltage ripple at Vin,
on the assumption that the voltage source feeding Vin has an
output impedance greater than zero. At maximum load cur-
rent, when the buck switch turns on, the current into pin 8 will
suddenly increase to the lower peak of the output current
waveform, ramp up to the peak value, then drop to zero at
CL
: When current limit is detected, the minimum off-time set
CC
UVLO at the buck switch on/off transi-
FB
= 2.5V. A standard value 316 kΩ
CC
OUT
output provides not only noise
is 100 mV/32 mA = 3.12Ω.
OUT
of 100 mV. Since the
CL
cal-
10
turn-off. The average input current during this on-time is the
load current (150 mA). For a worst case calculation, C1 must
supply this average load current during the maximum on-time.
To keep the input voltage ripple to less than 2V (for this ex-
ercise), C1 calculates to:
Quality ceramic capacitors in this value have a low ESR which
adds only a few millivolts to the ripple. It is the capacitance
which is dominant in this case. To allow for the capacitor’s
tolerance, temperature effects, and voltage effects, a 1.0 µF,
100V, X7R capacitor will be used.
C4: The recommended value is 0.01µF for C4, as this is ap-
propriate in the majority of applications. A high quality ceramic
capacitor, with low ESR is recommended as C4 supplies the
surge current to charge the buck switch gate at turn-on. A low
ESR also ensures a quick recharge during each off-time. At
minimum Vin, when the on-time is at maximum, it is possible
during start-up that C4 will not fully recharge during each 300
ns off-time. The circuit will not be able to complete the start-
up, and achieve output regulation. This can occur when the
frequency is intended to be low (e.g., R
C4 should be increased so it can maintain sufficient voltage
across the buck switch driver during each on-time.
C5: This capacitor helps avoid supply voltage transients and
ringing due to long lead inductance at V
ceramic chip capacitor is recommended, located close to the
SM72485.
FINAL CIRCUIT
The final circuit is shown in
and the resulting performance is shown in
6.
PC BOARD LAYOUT
The SM72485 regulation and over-voltage comparators are
very fast, and as such will respond to short duration noise
pulses. Layout considerations are therefore critical for opti-
mum performance. The components at pins 1, 2, 3, 5, and 6
should be as physically close as possible to the IC, thereby
minimizing noise pickup in the PC tracks. The current loop
formed by D1, L1, and C2 should be as small as possible. The
ground connection from D1 to C1 should be as short and di-
rect as possible.
If the internal dissipation of the SM72485 produces excessive
junction temperatures during normal operation, good use of
the pc board’s ground plane can help considerably to dissi-
pate heat. The exposed pad on the bottom of the LLP-8
package can be soldered to a ground plane on the PC board,
and that plane should extend out from beneath the IC to help
dissipate the heat. Additionally, the use of wide PC board
traces, where possible, can also help conduct heat away from
the IC. Judicious positioning of the PC board within the end
product, along with use of any available air flow (forced or
natural convection) can help reduce the junction tempera-
tures.
Figure
4. The circuit was tested,
T
IN
= 500K). In this case
Figure 5
. A low ESR, 0.1µF
and
Figure