ADNK-2080 Avago Technologies US Inc., ADNK-2080 Datasheet - Page 11

• Manufacturer Part Number: ADNK-2080
• Description: ADNS-2080 Sample Kit
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNK-2080

• Main Purpose: Reference Design, Optical Mouse
• Embedded: No
• Utilized Ic / Part: ADNS-2080
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Details
• Other names: 516-2296

Table 3. AC Electrical Specifications
Electrical characteristics over recommended operating conditions. Typical values at 25 °C, V
11
SDIO Hold Time
SDIO Timeout After Failure
Parameter
Motion Delay after Reset
Forced Rest Enable
Wake from Forced Rest
Power Down
Wake from Power Down
SDIO Rise Time
SDIO Fall Time
SDIO Delay after SCLK
SPI Time between Write
Commands
SPI Time between Write
and Read Commands
SPI Time between Read and
Subsequent Commands
SPI Read Address-
Data Delay
Transient Supply Current
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
t
t
I
r-SDIO
f-SDIO
DLY-SDIO
hold-SDIO
timeout-SDIO
DDT
MOT-RST
REST-EN
REST-DIS
PD
WAKEUP
SWW
SWR
SRW
SRR
SRAD
250
50
Min.
30
20
250
4
60
40
Typ.
200
200
120
Max.
50
1
1
50
55
1/f
60
SCLK
ns
ns
ns
ms
Units
ms
s
s
ms
ms
ns
Ps
Ps
ns
Ps
mA
C
C
From SCLK falling edge to SDIO data valid,
no load conditions
Notes
From RESET register write to valid motion
From Rest Mode(RM) bits set to target rest
mode
From Rest Mode(RM) bits cleared to valid
motion
From PD active (when bit 1 of register
0x0d is set) to low current
Through RESET register 0x3a.
From PD inactive to valid motion
Data held until next falling SCLK edge
Quiet time needed for the SPI block to
reset when it fails
From rising SCLK for last bit of the first
data byte, Commands to rising SCLK for
last bit of the second data byte
From rising SCLK f or last bit of the first
data byte, to rising SCLK for last bit of the
second address byte
From rising SCLK for last bit of the first
data byte, to falling SCLK for the first bit
of the next address
From rising SCLK for last bit of the address
byte, to falling SCLK for first bit of data
being read
Max supply current during a V
from 0 to V
20 ms rise time. (Does not include
charging currents for bypass capacitors.)
L
L
= 100 pF
= 100 pF
DDA
DDA
with min 150 Ps and max
= 2.2 V, V
DDIO
DDA
= 1.8 V.
ramp