AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet
AD9547/PCBZ
Specifications of AD9547/PCBZ
Related parts for AD9547/PCBZ
AD9547/PCBZ Summary of contents
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FEATURES Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair configurable as a single differential input or as ...
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AD9547 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Supply Voltage ............................................................................... 4 Supply Current .............................................................................. 4 Power Dissipation ......................................................................... 4 Logic Inputs ...
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Power Supply Partitions ............................................................. 98 Thermal Performance ................................................................. 98 Calculating the Digital Filter Coefficients ............................... 99 REVISION HISTORY 11/10—Rev Rev. B Changes to Pulse Width High, t Parameter, Table 17 and HIGH SCLK to Valid SDIO and SDO, ...
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AD9547 SPECIFICATIONS Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD = 1 SUPPLY VOLTAGE Table 1. Parameter ...
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LOGIC INPUTS (M0 TO M7, RESET) Table 4. Parameter INPUT VOLTAGE Input High Voltage ( Input Low Voltage ( INPUT CURRENT ( INH INL INPUT CAPACITANCE ( LOGIC OUTPUTS (M0 TO ...
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AD9547 Parameter Low Frequency Path Input Frequency Range Minimum Input Slew Rate Common-Mode Voltage Differential Input Voltage Sensitivity Input Capacitance Input Resistance Crystal Resonator Path Crystal Resonator Frequency Range Maximum Crystal Motional Resistance DISTRIBUTION CLOCK INPUTS (CLKINP, CLKINN) Table 7. ...
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REFERENCE INPUTS (REFA/REFAA, REFB/REFBB) Table 8. Parameter Min DIFFERENTIAL OPERATION Frequency Range Sinusoidal Input 10 LVPECL Input 0.001 LVDS Input 0.001 Minimum Input Slew Rate 40 Common-Mode Input Voltage Differential Input Voltage Sensitivity Input Resistance Input Capacitance Minimum Pulse Width ...
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AD9547 REFERENCE SWITCHOVER SPECIFICATIONS Table 10. Parameter MAXIMUM OUTPUT PHASE PERTURBATION (PHASE BUILD-OUT SWITCHOVER) MAXIMUM TIME/TIME SLOPE (HITLESS SWITCHOVER) TIME REQUIRED TO SWITCH TO A NEW REFERENCE Hitless Switchover Phase Build-Out Switchover the frequency of the active ...
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Parameter 1 Rise/Fall Time (20% to 80%) 3.3 V Supply Strong Drive Strength Setting Weak Drive Strength Setting 1.8 V Supply Duty Cycle Output Voltage High ( AVDD3 = 3 AVDD3 = ...
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AD9547 TIME DURATION OF DIGITAL FUNCTIONS Table 13. Parameter EEPROM-TO-REGISTER DOWNLOAD TIME REGISTER-TO-EEPROM UPLOAD TIME MINIMUM POWER-DOWN EXIT TIME MAXIMUM TIME FROM ASSERTION OF THE RESET PIN TO THE PINS ENTERING HIGH IMPEDANCE STATE DIGITAL PLL Table ...
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SERIAL PORT SPECIFICATIONS—SPI MODE Table 17. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input ...
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AD9547 SERIAL PORT SPECIFICATIONS—I Table 18. Parameter SDA (AS INPUT), SCL Input Logic 1 Voltage Input Logic 0 Voltage Input Current Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter ...
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JITTER GENERATION Table 19. Parameter 1 CONDITIONS kHz , f = 155.52 MHz REF DDS 100 Hz LOOP Bandwidth: 100 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to ...
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AD9547 ABSOLUTE MAXIMUM RATINGS Table 20. Parameter Rating Analog Supply Voltage (AVDD Digital Supply Voltage (DVDD Digital I/O Supply Voltage 3.6 V (DVDD3) DAC Supply Voltage (AVDD3) 3.6 V Maximum Digital Input Voltage −0 ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD SCLK/SCL CS/SDA DVDD DVDD3 DVDD RESET DVDD DVDD DACOUTP DACOUTN AVDD3 NOTES CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS). Table 21. Pin Function Descriptions Input/ Pin ...
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AD9547 Input/ Pin No. Output Pin Type 20 I Differential input 21 I Differential input 23 I Power 24 O Current set resistor 25 Power 26 O LVPECL, LVDS, or CMOS 27 O LVPECL, LVDS, or CMOS 28, ...
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Input/ Pin No. Output Pin Type 47 I Differential input 48 I Differential input Logic 54, 55, 56, 57, I/O 3.3 V CMOS 60, 61, 62 Exposed pad Mnemonic Description REFB Reference B ...
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AD9547 TYPICAL PERFORMANCE CHARACTERISTICS f = input reference clock frequency, f REF DPLL loop bandwidth, PLL off = SYSCLK PLL bypassed, PLL on = SYSCLK PLL enabled, I SYSCLK PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, ...
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INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 361fs (–69.0dBc) –80 20kHz TO 80MHz: 441fs (–67.3dBc) (EXTRAPOLATED) –90 –100 –110 –120 –130 –140 –150 –160 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) Figure 7. Additive Phase Noise (Output ...
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AD9547 1.0 0.8 LVPECL 0.6 0.4 LVDS 0 100 200 300 400 FREQUENCY (MHz) Figure 13. Amplitude vs. Toggle Rate, LVPECL and LVDS 4.0 3.5 10pF LOAD 3.0 2.5 20pF LOAD 2.0 1.5 1.0 0 100 200 300 ...
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LOAD 100 5pF LOAD 10pF LOAD 100 150 200 250 FREQUENCY (MHz) Figure 19. Power Consumption vs. Frequency, 3.3 V CMOS (Strong Mode) 1.0 0.8 0.6 0.4 0.2 0 –0.2 ...
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AD9547 2.0 1.5 20pF LOAD 1.0 0.5 0 –0 TIME (ns) Figure 25. Output Waveform, 1.8 V CMOS (100 MHz) 10pF LOAD Rev Page 22 of 104 ...
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INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF AD9547 HIGH IMPEDANCE 3.3V LVDS INPUT OUTPUT 0.1µF Figure 26. AC-Coupled LVDS or LVPECL Output Driver AD9547 3.3V LVPECL- COMPATIBLE OUTPUT Figure 27. DC-Coupled LVDS or LVPECL Output Driver 0.1µF AD9547 SELF-BIASED REFERENCE INPUT 0.1µF Figure ...
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AD9547 GETTING STARTED POWER-ON RESET The AD9547 monitors the voltage on the power supplies at power- up. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD (Pin 1, Pin 6, Pin 8, Pin 53, Pin 59, and ...
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Program the clock distribution outputs. The clock distribution parameters reside in the 0x0400 register address space. They include the following: • Output power-down control • Output enable (disabled by default) • Output synchronization • Output mode control • Output ...
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AD9547 THEORY OF OPERATION AD9547 DIFFERENTIAL OR SINGLE-ENDED REFA REFAA REFB REFBB INPUT REF MONITOR IRQ AND STATUS IRQ LOGIC OVERVIEW The AD9547 provides clocking outputs that are directly related in phase and frequency ...
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REFERENCE CLOCK INPUTS Two pairs of pins provide access to the reference clock receivers. Each pair is configurable either as a single differential receiver or as two independent single-ended receivers. To accommodate input signals with slow rising and falling edges, ...
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AD9547 REGISTER CONTROL BITS FORCE VALIDATION TIMEOUT REF MONITOR BYPASS REF MONITOR OVERRIDE REF FAULT REFERENCE MONITOR Reference Validation Override Control Register 0x0A0E to Register 0x0A10 provide the user with the ability to override the reference validation logic, enabling a ...
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Reference-to-Profile Assignment Control The user can manually assign a reference to a profile or let the device make the assignment automatically. The manual reference profile selection register (Address 0x0503 and Address 0x0504) is used to program whether a reference-to-profile assignment ...
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AD9547 As long as there are input references programmed for automatic profile assignment, and for which the profile assignment is null, the state machine continues to cycle through those references searching for a profile match. Furthermore, unless an input reference ...
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PRIORITY TABLE INPUT COMMON WITHOUT PROMOTION WITH PROMOTION PROFILE SELECTION REF A/REF AA REF B/REF BB Phase Build-Out Reference Switching Phase build-out reference switching is the term given to a ref- erence switchover that completely masks ...
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AD9547 DIGITAL PHASE-LOCKED LOOP (DPLL) CORE DPLL Overview A diagram of the digital PLL core of the AD9547 appears in Figure 35. The phase/frequency detector, feedback path, lock detectors, phase offset, and phase slew rate limiting that make up this ...
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Closed-Loop Phase Offset The all-digital nature of the TDC/PFD provides for numerical control of the phase offset between the reference and feedback edges. This allows the user to adjust the relative timing of the distribution output edges relative to the ...
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AD9547 During any given PFD phase error sample, the detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). The decision on whether to add or remove water ...
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DDS Phase Offset The relative phase of the sinusoid generated by the DDS is numer- ically controlled by adding a phase offset word to the output of the DDS accumulator. This is accomplished via the open loop phase offset register ...
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AD9547 Note that history accumulation timer = 0 should not be pro- grammed because it may cause improper device operation. The control logic performs a calculation of the average tuning word during the T interval and stores the result in ...
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Recovery from Holdover When in holdover valid reference becomes available, the device exits holdover operation. The loop state machine restores the DPLL to closed-loop operation, locks to the selected reference, and sequences the recovery of all the loop ...
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AD9547 LF XTAL SYSCLKN 37 SYSCLKP 38 HF The LF path permits the user to provide an LVPECL, LVDS, CMOS, or sinusoidal low frequency clock for multiplication by the integrated SYSCLK PLL. The LF path handles input frequencies from 3.5 ...
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Charge Pump The charge pump operates in either automatic or manual mode, based on the charge pump mode bit (Register 0x0100, Bit 6). When Register 0x0100, Bit the AD9547 automatically selects the appropriate charge pump current based ...
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AD9547 CLOCK DISTRIBUTION The clock distribution block of the AD9547 provides an integrated solution for generating multiple clock outputs based on frequency dividing the DPLL output. The distribution output consists of two channels (OUT0 and OUT1). Each channel has a ...
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Output Mode The user has independent control of the operating mode of each of the two output channels via the distribution channel modes register (Address 0x0404 and Address 0x0405). The operating mode control includes • Logic family and pin functionality ...
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AD9547 The synchronization event is the clearing operation; that is, the Logic 1 to Logic 0 transition of the bit. The primary synchronization signal can synchronize the distri- bution output directly can enable a secondary synchronization signal. This ...
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The deterministic delay, expressed as t LATENCY equation function of the frequency division factor (Q the channel divider associated with the zero-delay channel × LATENCY n CLK_IN LATENCY In addition ...
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AD9547 STATUS AND CONTROL MULTIFUNCTION PINS (M0 TO M7) The AD9547 has eight digital CMOS I/O pins (M0 to M7) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each ...
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At power-up, the multifunction pins can be used to force the device into certain configurations as defined in the Initial Pin Programming section. This functionality, however, is valid only during power-up or following a reset, after which ...
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AD9547 EEPROM EEPROM Overview The AD9547 contains an integrated 2048-byte electrically erasable programmable read-only memory (EEPROM). The AD9547 can be configured to perform a download at power-up via the multifunction pins (M3 to M7), but uploads and downloads can also ...
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Table 27. EEPROM Controller Instruction Set Instruction Bytes Value (Hex) Instruction Type Required 0x00 to 0x7F Data 3 0x80 I/O update 1 0xA0 Calibrate 1 0xA1 Distribution sync 1 0xB0 to 0xCF Condition 1 0xFE Pause 1 0xFF End 1 ...
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AD9547 Automatic EEPROM Download Following power-up, assertion of the RESET pin soft reset (Register 0x0000, Bit 5 = 1), if FncInit[7:3] ≠ 0 (see the Initial Pin Programming section), the instruction sequence stored in the ...
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If the condition is not tagged, the controller skips instructions until it encounters a condition instruction that decodes as a tagged condition. Note that the condition tag board allows for multiple conditions to be tagged at any given moment. This ...
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AD9547 SERIAL CONTROL PORT SCLK/SCL CS/SDA SDIO SDO The AD9547 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9547 serial control port is compatible with most ...
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SPI Mode Operation The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. By default, the AD9547 uses the bidirectional MSB-first ...
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AD9547 SPI Instruction Word (16 Bits) The MSB of the 16-bit instruction word is R/ whether the instruction is a read or a write. The next two bits, W1 and W0, indicate the number of bytes in the transfer (see ...
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SCLK SDIO CS SCLK DON'T CARE A10 A11 A12 SDIO DON'T CARE 16-BIT INSTRUCTION HEADER Figure 55. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data t CS ...
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AD9547 I²C SERIAL PORT OPERATION 2 The I C interface has the advantage of requiring only two control pins and facto standard throughout the I industry. However, its disadvantage is programming speed, which is 400 kbps maximum. ...
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Data Transfer Process The master initiates data transfer by asserting a start condition. This indicates that a data stream follows. All I2C slave devices connected to the serial bus respond to the start condition. The master then sends an 8-bit ...
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AD9547 I²C Serial Port Timing SDA t t LOW SCL t HD;STA t S HD;DAT Table 35. I2C Timing Definitions Parameter Description f Serial clock SCL t Bus free time between stop and start conditions BUF t ...
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I/O PROGRAMMING REGISTERS The register map spans an address range from 0x0000 through 0x0E3F (0 to 3647, decimal). Each address provides access to one byte (eight bits) of data. Each individual register is iden- tified by its four-digit hexadecimal address ...
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AD9547 REGISTER MAP The register addresses and defaults are hexadecimal values. Use the default value when writing to registers and/or bits marked as unused. Table 36. 1 Addr Opt Name D7 Serial Port Configuration and Part Identification 0x0000 E SPI ...
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Addr Opt 1 Name D7 DPLL 0x0300 C Free-running frequency 0x0301 C tuning word 0x0302 C 0x0303 C 0x0304 C 0x0305 C 0x0306 A, C Update TW 0x0307 C Pull-in range lower limit 0x0308 C 0x0309 C 0x030A C Pull-in ...
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AD9547 Addr Opt 1 Name D7 0x0410 S Reserved 0x0411 S 0x0412 S 0x0413 S 0x0414 S 0x0415 S 0x0416 S 0x0417 S Reference Input Configuration 0x0500 S Reference power-down 0x0501 S Reference Ref BB logic family[1:0] logic family 0x0502 ...
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Addr Opt 1 Name D7 0x061E R divider 0x061F 0x0620 0x0621 Unused 0x0622 S divider 0x0623 0x0624 0x0625 0x0626 Fractional feedback 0x0627 divider 0x0628 Unused 0x0629 Lock detectors 0x062A 0x062B 0x062C 0x062D 0x062E 0x062F 0x0630 0x0631 Profile Registers—Profile 1 0x0632 ...
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AD9547 Addr Opt 1 Name D7 0x0650 R divider 0x0651 0x0652 0x0653 Unused 0x0654 S divider 0x0655 0x0656 0x0657 0x0658 Fractional feedback 0x0659 divider 0x065A Unused 0x065B Lock detectors 0x065C 0x065D 0x065E 0x065F 0x0660 0x0661 0x0662 0x0663 0x0664 Unused to ...
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Addr Opt 1 Name D7 0x069E R divider 0x069F 0x06A0 0x06A1 Unused 0x06A2 S divider 0x06A3 0x06A4 0x06A5 0x06A6 Fractional feedback 0x06A7 divider 0x06A8 Unused 0x06A9 Lock detectors 0x06AA 0x06AB 0x06AC 0x06AD 0x06AE 0x06AF 0x06B0 0x06B1 Profile Registers—Profile 3 0x06B2 ...
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AD9547 Addr Opt 1 Name D7 0x06D4 S divider 0x06D5 0x06D6 0x06D7 0x06D8 Fractional feedback 0x06D9 divider 0x06DA Unused 0x06DB Lock detectors 0x06DC 0x06D D 0x06DE 0x06DF 0x06E0 0x06E1 0x06E2 0x06E3 0x06E4 to 0x06FF Profile Registers—Profile 4 through Profile 7 ...
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Addr Opt 1 Name D7 Status Readback (These registers are read only and are accessible during EEPROM transactions.) 0x0D00 R EEPROM 0x0D01 R SYSCLK 0x0D02 R IRQ monitor Unused 0x0D03 R 0x0D04 R Switching 0x0D05 R 0x0D06 R Ref AA ...
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AD9547 Addr Opt 1 Name D7 0x0E19 E 0x0E1A E 0x0E1B E Clock distribution 0x0E1C E settings 0x0E1D E 0x0E1E E I/O update 0x0E1F E Reference input settings 0x0E20 E 0x0E21 E 0x0E22 E Profile 0 and Profile 1 0x0E23 ...
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REGISTER BIT DESCRIPTIONS SERIAL PORT CONFIGURATION AND PART IDENTIFICATION (REGISTER 0x0000 TO REGISTER 0x0005) 2 Table 37. SPI Control/I C Control Address Bit Bit Name 0x0000 7 Unidirectional 6 LSB first/IncAddr 5 Soft reset 4 Long instruction [3:0] Unused Table ...
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AD9547 SYSTEM CLOCK (SYSCLK) (REGISTER 0x0100 TO REGISTER 0x0108) Table 43. Charge Pump and Lock Detect Control Address Bit Bit Name 0x0100 7 External loop filter enable 6 Charge pump mode [5:3] Charge pump current 2 Lock detect timer disable ...
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Table 46. Nominal System Clock (SYSCLK) Period Address Bit Bit Name 0x0103 [7:0] Nominal SYSCLK period (expressed in fs) 0x0104 [7:0] 0x0105 [7:5] Unused [4:0] Nominal SYSCLK period 1 Units are femtoseconds (fs). The default value is 0x0F424 = 1,000,000 ...
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AD9547 Register 0x0209 to Register 0x0210—IRQ Mask The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0x0D02 to Address 0x0D09). When set to Logic 1, the IRQ mask bits enable the ...
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Table 54. IRQ Mask for Reference Inputs Address Bit Bit Name 0x020D 7 Ref AA new profile 6 Ref AA validated 5 Ref AA fault cleared 4 Ref AA fault 3 Ref A new profile 2 Ref A validated 1 ...
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AD9547 DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B) Table 57. Free-Running Frequency Tuning Word Address Bit Bit Name 0x0300 [7:0] Free-running frequency tuning word (expressed as a 48-bit frequency 0x0301 [7:0] tuning word) 0x0302 [7:0] 0x0303 [7:0] 0x0304 [7:0] 0x0305 ...
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Table 62. Incremental Closed-Loop Phase Lock Offset Step Size Address Bit Bit Name 0x0314 [7:0] Incremental phase lock offset step size (expressed in ps/step) 0x0315 [7:0] 1 The default incremental closed loop phase lock offset step size value is 0x03E8 ...
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AD9547 CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0417) 1 Table 66. Distribution Settings Address Bit Bit Name 0x0400 [7:6] Unused 5 External distribution resistor 4 Receiver mode [3:2] Unused 1 OUT1 power-down 0 OUT0 power-down 1 When Bits ...
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Table 70. Distribution Channel Modes Address Bit Bit Name 0x0404 [7:6] Unused 5 OUT0 CMOS phase invert 4 OUT0 polarity invert 3 OUT0 drive strength [2:0] OUT0 mode 0x0405 [7:6] Unused 5 OUT1 CMOS phase invert 4 OUT1 polarity invert ...
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AD9547 Register 0x0408 to Register 0x0417—Distribution Channel Dividers 1 Table 71. Q0 Divider Address Bit Bit Name 0x0408 [7:0] Q0 0x0409 [7:0] 0x040A [7:0] 0x040B [7:6] Unused [5: The default value is 0 (or divide by 1). 1 ...
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Table 75. Reference Logic Family Address Bit Bit Name 0x0501 [7:6] Ref BB logic family [5:4] Ref B logic family [3:2] Ref AA logic family [1:0] Ref A logic family 0x0502 [7:0] Unused Table 76. Manual Reference Profile Selection Address ...
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AD9547 PROFILE REGISTERS (REGISTER 0x0600 TO REGISTER 0x07FF) Note that the default value of every bit is 0 for Profile 0 to Profile 7. Register 0x0600 to Register 0x0631—Profile 0 Table 78. Priorities—Profile 0 Address Bit Bit Name 0x0600 [7] ...
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Table 83. Digital Loop Filter Coefficients—Profile 0 Address Bit Bit Name 0x0612 [7:0] Alpha-0 linear 0x0613 [7:0] 0x0614 [7:6] Alpha-2 exponent [5:0] Alpha-1 exponent 0x0615 [7:1] Beta-0 linear 0 Alpha-2 exponent 0x0616 [7:0] Beta-0 linear 0x0617 7 Unused [6:2] Beta-1 ...
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AD9547 Table 86. Fractional Feedback Divider—Profile 0 Address Bit Bit Name 0x0626 [7:0] V 0x0627 [7:4] U [3:2] Unused [1:0] V 0x0628 [7:6] Unused [5:0] U Table 87. Lock Detectors—Profile 0 Address Bit Bit Name 0x0629 [7:0] Phase lock threshold ...
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Address Bit Bit Name 0x063F [7:4] Unused [3:0] Outer tolerance Table 91. Validation Timer—Profile 1 Address Bit Bit Name 0x0640 [7:0] Validation timer (expressed in units of ms) 0x0641 [7:0] Table 92. Redetect Timer—Profile 1 Address Bit Bit Name 0x0642 ...
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AD9547 1 Table 95. S Divider—Profile 1 Address Bit Bit Name 0x0654 [7:0] S 0x0655 [7:0] S 0x0656 [7:4] Unused [3:0] S 0x0657 [7:0] Unused 1 The value stored in the S divider register yields an actual divide ratio of ...
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Table 100. Tolerance—Profile 2 Address Bit Bit Name 0x0688 [7:0] Inner tolerance 0x0689 [7:0] 0x068A [7:4] Unused [3:0] Inner tolerance 0x068B [7:0] Outer tolerance 0x068C [7:0] 0x068D [7:4] Unused [3:0] Outer tolerance Table 101. Validation Timer—Profile 2 Address Bit Bit ...
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AD9547 Register 0x069E to Register 0x06A8—Profile 2 Frequency Multiplication 1 Table 104. R Divider—Profile 2 Address Bit Bit Name 0x069E [7:0] R 0x069F [7:0] 0x06A0 [7:0] 0x06A1 [7:6] Unused [5: The value stored in the R divider register ...
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Register 0x06B2 to Register 0x06FF—Profile 3 Table 108. Priorities—Profile 3 Address Bit Bit Name 0x06B2 [7] Phase lock scale [6] Unused [5:3] Promoted priority [2:0] Selection priority Table 109. Reference Period—Profile 3 Address Bit Bit Name 0x06B3 [7:0] Reference period ...
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AD9547 Address Bit Bit Name 0x06C8 [7:0] Beta-0 linear 0x06C9 7 Unused [6:2] Beta-1 exponent [1:0] Beta-0 linear 0x06CA [7:0] Gamma-0 linear 0x06CB [7:0] 0x06CC [7:6] Unused [5:1] Gamma-1 exponent 0 Gamma-0 linear 0x06CD [7:0] Delta-0 linear 0x06CE 7 Delta-1 ...
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Table 117. Lock Detectors—Profile 3 Address Bit Bit Name 0x06DB [7:0] Phase lock threshold (units determined by Register 0x06B2[7]) 0x06DC [7:0] 0x06DD [7:0] Phase lock fill rate 0x06DE [7:0] Phase lock drain rate 0x06DF [7:0] Frequency lock threshold (expressed in ...
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AD9547 OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10) Table 118. General Power-Down Address Bit Bit Name 0x0A00 7 Reset sans regmap 6 Unused 5 SYSCLK power-down 4 Reference power-down 3 TDC power-down 2 DAC power-down 1 Dist power-down 0 Full ...
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Table 120. Cal/Sync Address Bit Bit Name 0x0A02 [7:2] Unused 1 Sync distribution 0 Calibrate SYSCLK Register 0x0A03—Reset Functions 1 Table 121. Reset Functions Address Bit Bit Name 0x0A03 7 Unused 6 Clear LF 5 Clear CCI 4 Clear phase ...
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AD9547 Table 124. IRQ Clearing for the Digital PLL Address Bit Bit Name 0x0A06 7 Switching 6 Closed 5 Free run 4 Holdover 3 Frequency unlocked 2 Frequency locked 1 Phase unlocked 0 Phase locked Table 125. IRQ Clearing for ...
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Table 127. Incremental Phase Offset Control Address Bit Bit Name 0x0A0C [7:3] Unused 2 Reset phase offset 1 Decrement phase offset 0 Increment phase offset Table 128. Reference Profile Selection State Machine Startup Address Bit Bit Name 0x0A0D [7:4] Unused ...
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AD9547 STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D19) All bits in Register 0x0D00 to Register 0x0D19 are read only. These registers are accessible during EEPROM transactions. Table 132. EEPROM Status Address Bit Bit Name 0x0D00 [7:3] Unused 2 Fault detected ...
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Table 137. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit Address Bit Bit Name 0x0D05 [7:5] Unused 4 History updated 3 Frequency unclamped 2 Frequency clamped 1 Phase slew unlimited 0 Phase slew limited Table 138. IRQ ...
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AD9547 Table 140. Input Reference Status Address Bit Bit Name 0x0D0C 7 Profile selected [6:4] Selected profile 3 Valid 2 Fault 1 Fast 0 Slow 0x0D0D [7:0] 0x0D0E [7:0] 0x0D0F [7:0] 0x0D10 [7:0] Unused 0x0D11 [7:0] 0x0D12 [7:0] 0x0D13 [7:0] ...
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Table 145. Load Address Bit Bit Name 0x0E03 [7:2] Unused 1 Load from EEPROM 0 Unused EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3F) The default settings of Register 0x0E10 to Register 0x0E33 embody a sample scratch pad instruction sequence. ...
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AD9547 Table 150. EEPROM Storage Sequence for Clock Distribution Settings Address Bit Bit Name 0x0E1B [7:0] Clock distribution 0x0E1C [7:0] Clock distribution 0x0E1D [7:0] 0x0E1E [7:0] I/O update Table 151. EEPROM Storage Sequence for Reference Input Settings Address Bit Bit ...
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Table 154. EEPROM Storage Sequence for Profile 4 and Profile 5 Settings Address Bit Bit Name 0x0E28 [7:0] Profile 4 and Profile 5 0x0E29 [7:0] Profile 4 and Profile 5 0x0E2A [7:0] Table 155. EEPROM Storage Sequence for Profile 6 ...
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AD9547 APPLICATIONS INFORMATION POWER SUPPLY PARTITIONS The AD9547 features multiple power supplies, and their power consumption varies with the AD9547 configuration. This section provides information about which power supplies can be grouped together and how the power consumption of each ...
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CALCULATING THE DIGITAL FILTER COEFFICIENTS The digital loop filter coefficients (α, β, γ, and δ, as shown in Figure 38) relate to the time constants (T associated with the equivalent analog circuit for a third-order loop filter (see Figure 64). ...
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AD9547 The min() function y = min ... where: x through list of real numbers the number in the list that is the farthest to ...
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Calculation of the β Register Values The quantized β coefficient consists of two components, β β , according to 1 −(17 + β ) −β ≈ β = β × quantized 0 where β and β are the ...
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... PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9547BCPZ −40°C to +85°C AD9547BCPZ-REEL7 −40°C to +85°C AD9547/PCBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ 0. ...
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NOTES Rev Page 103 of 104 AD9547 ...
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AD9547 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08300-0-11/10(B) Rev Page 104 of 104 ...