AD9957/PCBZ Analog Devices Inc, AD9957/PCBZ Datasheet
AD9957/PCBZ
Specifications of AD9957/PCBZ
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AD9957/PCBZ Summary of contents
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FEATURES 1 GSPS internal clock speed (up to 400 MHz analog output) Integrated 1 GSPS 14-bit DAC 250 MSPS input data rate Phase noise ≤ −125 dBc/Hz (400 MHz carrier @ 1 kHz offset) Excellent dynamic performance >80 dB narrow-band ...
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AD9957 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 4 Specifications ..................................................................................... 5 Electrical Specifications ............................................................... 5 Absolute Maximum Ratings ............................................................ 8 ESD Caution .................................................................................. 8 Pin ...
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Sync Generator ............................................................................ 40 Sync Receiver ............................................................................... 41 Setup/Hold Validation ................................................................ 42 Synchronization Example .......................................................... 44 I/Q Path Latency ......................................................................... 45 Example .................................................................................... 45 Power Supply Partitioning ............................................................. 46 3.3 V Supplies .............................................................................. 46 DVDD_I/O (Pin 11, Pin 15, Pin ...
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AD9957 REVISION HISTORY 10/10—Rev Rev. B Changes to Data Rate in Features Section ..................................... 1 Changes to Specifications Section .................................................. 6 Added EPAD Notation to Figure 4 and Table 3............................ 9 Changes to XTAL_SEL Pin Description ...................................... 11 ...
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SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD (3.3V) = 3.3 V ± 5%, DVDD_I/O (3.3V) = 3.3 V ± 5 25° mA, external reference clock frequency = ...
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AD9957 Parameter NOISE SPECTRAL DENSITY (NSD) Single Tone f = 20.1 MHz OUT f = 98.6 MHz OUT f = 201.1 MHz OUT f = 397.8 MHz OUT TWO-TONE INTERMODULATION DISTORTION (IMD MHz OUT ...
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Parameter CMOS LOGIC INPUTS Voltage Logic 1 Logic 0 Current Logic 1 Logic 0 Input Capacitance XTAL_SEL INPUT Logic 1 Voltage Logic 0 Voltage Input Capacitance CMOS LOGIC OUTPUTS Voltage Logic 1 Logic 0 POWER SUPPLY CURRENT DVDD_I/O (3.3V) Pin ...
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AD9957 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter AVDD (1.8V), DVDD (1.8V) Supplies AVDD (3.3V), DVDD_I/O (3.3V) Supplies Digital Input Voltage XTAL_SEL Digital Output Current Storage Temperature Range Operating Temperature Range θ JA θ JC Maximum Junction Temperature Lead Temperature, Soldering ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 PLL_LOOP_FILTER 2 AVDD (1.8V) 3 AGND 4 AGND 5 AVDD (1.8V) 6 SYNC_IN+ 7 SYNC_IN– 8 SYNC_OUT+ 9 SYNC_OUT– 10 DVDD_I/O (3.3V) 11 SYNC_SMP_ERR 12 DGND 13 MASTER_RESET 14 DVDD_I/O (3.3V) 15 DGND ...
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AD9957 Table 3. Pin Function Descriptions Pin No. Mnemonic 1, 24, 61, 72, 86, NC 87, 93 100 2 PLL_LOOP_FILTER 3, 6, 89, 92 AVDD (1.8V 77, 83 AVDD (3.3V) 17, 23, 30, 47, 57, DVDD ...
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Pin No. Mnemonic 59 I/O_UPDATE 60 OSK 67 SDIO 68 SDO 69 SCLK I/O_RESET 80 IOUT 81 IOUT 84 DAC_RSET 90 REF_CLK 91 REF_CLK 94 REFCLK_OUT 95 XTAL_SEL 96 (EPAD) Exposed Pad (EPAD input, ...
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AD9957 TYPICAL PERFORMANCE CHARACTERISTICS 1 0 –10 –20 –30 –40 –50 –60 1 –70 –80 –90 –100 START 0Hz 50MHz/DIV Figure 5. 15.625 kHz Quadrature Tone, Carrier = 102 MHz, CCI = 16 GHz ...
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START 0Hz 50MHz/DIV Figure 11. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, α = 0.25, CCI = 8, Carrier = 102 MHz –10 –20 –30 –40 –50 ...
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AD9957 –50 –55 SFDR WITHOUT PLL –60 –65 –70 – 100 150 200 FREQUENCY OUT (MHz) Figure 17. Wideband SFDR vs. Output Frequency in Single Tone Mode, PLL with REFCLK = 15.625 MHz × 64 –45 –50 HIGH ...
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DVDD 1.8V 800 600 400 AVDD 3.3V DVDD 3.3V 200 0 400 500 600 700 800 SYSTEM CLOCK FREQUENCY (MHz) Figure 23. Power Dissipation vs. System Clock (PLL Enabled) –20 –30 –40 –50 –60 –70 –80 –90 AVDD ...
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AD9957 MODES OF OPERATION OVERVIEW The AD9957 has three basic operating modes. • Quadrature modulation (QDUC) mode (default) • Interpolating DAC mode • Single tone mode The active mode is selected via the operating mode bits in Control Function Register ...
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QUADRATURE MODULATION MODE A block diagram of the AD9957 operating in QDUC mode is shown in Figure 26; grayed items are inactive. The parallel input accepts 18-bit I- and Q-words in time-interleaved fashion. That is, an 18-bit I-word is followed ...
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AD9957 BLACKFIN INTERFACE (BFI) MODE A subset of the QDUC mode is the Blackfin interface (BFI) mode, shown in Figure 27; grayed items are inactive. In this mode, a separate I and Q serial bit stream is applied to the ...
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INTERPOLATING DAC MODE A block diagram of the AD9957 operating in interpolating DAC mode is shown in Figure 28; grayed items are inactive. In this mode, the Q data path, DDS, and modulator are all disabled; only the I data ...
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AD9957 SINGLE TONE MODE A block diagram of the AD9957 operating in single tone mode is shown in Figure 29; grayed items are inactive. In this mode, both I and Q data paths are disabled from the 18-bit parallel data ...
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SIGNAL PROCESSING For a better understanding of the operation of the AD9957 helpful to follow the signal path in quadrature modulation mode from the parallel data port to the output of the DAC, examining the function of each ...
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AD9957 TxENABLE t DS PDCLK D<17:0> Figure 30. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode TxENABLE t DS PDCLK D<17:0> Figure 31. 18-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode TxENABLE ...
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Encoding and pulse shaping of symbols must be implemented before the data is presented to the input of the AD9957. Data delivered to the input of the AD9957 may be formatted as either twos complement or offset binary (see the ...
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AD9957 Knowledge of the frequency response of the half-band filters is essential to understanding their impact on the spectral properties of the input signal. This is especially true when using the quad- rature modulator to upconvert a baseband signal containing ...
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QUADRATURE MODULATOR The digital quadrature modulator stage shifts the frequency of the baseband spectrum of the incoming data stream up to the desired carrier frequency (a process known as upconversion). At this point, the baseband data, which was delivered to ...
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AD9957 In Figure 37, it can be seen that the sinc envelope introduces a frequency dependent attenuation that can be as much the Nyquist frequency (half of the DAC sample rate). Without the inverse sinc filter, ...
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RAM CONTROL RAM OVERVIEW The AD9957 has an integrated 1024 × 32-bit RAM. This RAM is only accessible when the AD9957 is operating in QDUC or interpolating DAC mode. The RAM has two fundamental modes of operation: data entry/retrieve mode ...
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AD9957 LOAD/RETRIEVE RAM OPERATION Loading or retrieving the RAM contents is a three-step process. 1. Program the RAM segment registers with start and end addresses defining the boundaries of each independent RAM segment. 2. Toggle the RT pin with the ...
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RAM MODE 16 ADDRESS STEP RATE 10 START ADDRESS 10 END ADDRESS DDS CLOCK BASEBAND DATA CLOCK CLK U STATE Q RAM MACHINE UP/DOWN COUNTER CHANNEL IS (MSBs CHANNEL 16 QS (LSBs) ...
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AD9957 RAM Bidirectional Ramp Mode This mode is unique in that the RAM segment playback mode word of both RAM segment registers must be programmed for RAM bidirectional ramp mode. In bidirectional ramp mode, upon assertion of an I/O update, ...
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The circled numbers in Figure 44 indicate specific events, explained as follows: Event 1—an I/O update or profile change activates the RAM bidirectional ramp mode. Event 2—the RT pin switches to Logic 1. The state machine initializes to the start ...
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AD9957 1 PDCLK CYCLE M DDS CLOCK CYCLES RAM ADDRESS I/O_UPDATE OR RT TRANSITION RAM Continuous Bidirectional Ramp Mode In continuous bidirectional ramp mode, upon assertion of an I/O update or a state change on the RT pin, the RAM ...
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PDCLK CYCLE M DDS CLOCK CYCLES RAM ADRESS I/O_UPDATE OR RT TRANSITION 1 RAM Continuous Recirculate Mode The continuous recirculate mode mimics ramp-up mode, except that when the state machine reaches the end address of the active RAM segment ...
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AD9957 CLOCK INPUT (REF_CLK) REFCLK OVERVIEW The AD9957 supports a number of options for producing the internal SYSCLK signal (that is, the DAC sample clock) via the REF_CLK/ REF_CLK input pins. The REF_CLK input can be driven directly from a ...
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PECL, LVPECL, DIFFERENTIAL SOURCE, OR TERMINATION DIFFERENTIAL INPUT. LVDS DRIVER BALUN (1:1) SINGLE-ENDED SOURCE, DIFFERENTIAL INPUT. SINGLE-ENDED SOURCE, 50Ω SINGLE-ENDED INPUT. Figure 49. Direct Connection Diagram PHASE-LOCKED LOOP (PLL) MULTIPLIER An internal phase-locked loop (PLL) provides users of the AD9957 ...
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AD9957 PLL CHARGE PUMP The charge pump current ( programmable to provide the CP user with additional flexibility to optimize the PLL performance. Table 8 lists the bit settings vs. the nominal charge pump current. Table 8. PLL ...
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ADDITIONAL FEATURES OUTPUT SHIFT KEYING (OSK) The OSK function (Figure 53) is only available in single tone mode. It allows the user to control the output signal amplitude of the DDS. Both manual and automatic modes are available. OSK 60 ...
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AD9957 Table 9. OSK Amplitude Step Size ASF<1:0> Amplitude Step Size mentioned earlier, the step interval is controlled by a 16-bit programmable timer. Normally, this timer is loaded with the programmed ...
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POWER-DOWN CONTROL The AD9957 offers the ability to independently power down four specific sections of the device. Power-down functionality applies to the digital core, DAC, auxiliary DAC, and REFCLK input. A power-down of the digital core disables the ability to ...
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AD9957 SYNCHRONIZATION OF MULTIPLE DEVICES OVERVIEW The internal clocks of the AD9957 provide the timing for the propagation of data along the baseband signal processing path. These internal clocks are derived from the internal system clock (SYSCLK) and are all ...
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PROGAMMABLE D Q SYSCLK DELAY ÷16 ÷ SYNC 1 GENERATOR DELAY SYNC POLARITY SYNC GENERATOR ENABLE Figure 56. Sync Generator The sync generator produces an LVDS-compatible clock signal with a 50% duty cycle that appears at the ...
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AD9957 SYNC_IN+ SYNC_IN– SYNC_SMP_ERR When a device other than another AD9957 provides the SYNC_IN signal it must be LVDS compatible. Furthermore, although SYNC_IN is typically considered periodic clock signal not an absolute requirement ...
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The validation result latch reset state whenever the sync receiver is disabled, which forces the SYNC_SMP_ERR pin to a Logic 0 state. To reset the validation result latch when the sync receiver is active, however, requires the ...
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AD9957 SYNCHRONIZATION EXAMPLE To accomplish the synchronization of multiple devices provide each AD9957 with a SYNC_IN signal that is edge aligned across all the devices. If the SYNC_IN signal is edge aligned at all devices, and all devices have the ...
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I/Q PATH LATENCY The I/Q latency through the AD9957 is easiest to describe in terms of system clock (SYSCLK) cycles and is a function of the AD9957 configuration (that is, which mode and which optional features are engaged). The I/Q ...
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AD9957 POWER SUPPLY PARTITIONING The AD9957 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. The ...
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SERIAL PROGRAMMING CONTROL INTERFACE—SERIAL I/O The AD9957 serial port is a flexible, synchronous serial commu- nications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9957. MSB-first or ...
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AD9957 SDO—Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9957 operates in a single bidirectional I/O mode, this pin does not output data ...
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I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK RELATIONSHIPS The I/O_UPDATE pin is used to transfer data from the serial I/O buffer to the active registers in the device. Data in the buffer is inactive. SYNC_CLK is a rising edge active signal. It ...
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AD9957 REGISTER MAP AND BIT DESCRIPTIONS REGISTER MAP Note that the highest number found in the Bit Range column for each register in the following tables is the MSB and the lowest number is the LSB for that register. Table ...
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Table 14. RAM, ASF, Multichip Sync, and Profile 0 Registers Bit Range Register Name (Internal Bit 7 (Serial Address) Address) (MSB) RAM Segment <47:40> Register 0 (0x05) <39:32> <31:24> <23:16> RAM End Address 0<1:0> <15:8> <7:0> RAM Start Address 0<1:0> ...
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AD9957 Table 15. Profile 1, Profile 2, and Profile 3 Registers Register Name Bit Range Bit 7 (Serial (Internal Address) Address) (MSB) Profile 1 <63:56> Register— <55:48> Single Tone <47:40> (0x0F) <39:32> <31:24> <23:16> <15:8> <7:0> Profile 1 <63:56> Register— ...
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Table 16. Profile 4, Profile 5, and Profile 6 Registers Register Bit Name Range (Serial (Internal Address) Address) Bit 7 (MSB) Profile 4 <63:56> Open Register— <55:48> Single Tone <47:40> (0x12) <39:32> <31:24> <23:16> <15:8> <7:0> Profile 4 <63:56> Register— ...
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AD9957 Table 17. Profile 7, RAM, GPIO Configuration, and GPIO Data Registers Bit Range Register Name (Internal (Serial Address) Address) Profile 7 <63:56> Register— <55:48> Single Tone <47:40> (0x15) <39:32> <31:24> <23:16> <15:8> <7:0> Profile 7 <63:56> Register— QDUC (0x15) ...
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REGISTER BIT DESCRIPTIONS The serial I/O port registers span an address range (0x00 to 0x19 in hexadecimal notation). This represents a total of 26 registers. However, six of these registers are unused, yielding a total of ...
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AD9957 Bit (s) Mnemonic Description 9 OSK (Output Shift 0: OSK disabled (default). Keying) Enable 1: OSK enabled. 8 Select Auto-OSK Ineffective unless CFR1<9> manual OSK enabled (default). 1: automatic OSK enabled. 7 Digital Power- This bit ...
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Bit (s) Mnemonic Description 21:17 Open 16 Read Effective 0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default). FTW 1: a serial I/O port read operation of the FTW register ...
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AD9957 Control Function Register 3 (CFR3) Address 0x02, four bytes are assigned to this register. Table 20. Bit Descriptions for CFR3 Register Bit (s) Mnemonic Description 31:30 Open 29:28 DRV0 Controls REFCLK_OUT pin (see Table 6 for details); default is ...
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RAM Segment Register 1 Address 0x06, six bytes are assigned to this register. This register is only active if CFR1<31> and there is a Logic 1 to Logic 0 transition on the RT pin. Table 24. Bit Descriptions ...
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AD9957 PROFILE REGISTERS There are eight consecutive serial I/O addresses (0x0E to 0x15) dedicated to device profiles. All eight profile registers are either single tone profiles or QDUC profiles depending on the device operating mode specified by CFR1<25:24>. During operation, ...
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... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE 1 Model Temperature Range AD9957BSVZ −40°C to +85°C AD9957BSVZ-REEL −40°C to +85°C AD9957/PCBZ RoHS Compliant Part. 16.00 BSC SQ 14.00 BSC 100 PIN 1 TOP VIEW (PINS DOWN ...
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AD9957 NOTES Rev Page ...
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NOTES Rev Page AD9957 ...
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AD9957 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06384-0-10/10(B) Rev Page ...