AD9552/PCBZ Analog Devices Inc, AD9552/PCBZ Datasheet
AD9552/PCBZ
Specifications of AD9552/PCBZ
Related parts for AD9552/PCBZ
AD9552/PCBZ Summary of contents
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FEATURES Converts a low frequency input reference signal to a high frequency output signal Input frequencies from 6.6 MHz to 112.5 MHz Output frequencies up to 900 MHz Preset pin programmable frequency translation ratios Arbitrary frequency translation ratios via SPI ...
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AD9552 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Basic Block Diagram ........................................................................ 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Crystal Input Characteristics ...................................................... 4 Output Characteristics ................................................................. 4 Jitter Characteristics ..................................................................... 5 Serial ...
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SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD = 3 25°C, unless otherwise noted. A Table 1. Parameter Min SUPPLY ...
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AD9552 Parameter Min Input Capacitance Input Resistance Duty Cycle 40 Input Voltage Input High Voltage, V 0.52 IH Input Low Voltage Input Threshold Voltage VCO CHARACTERISTICS Frequency Range Upper Bound Lower Bound VCO Gain VCO Tracking Range ±300 ...
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Parameter LVDS MODE Differential Output Voltage Swing Balanced Unbalanced, ΔV OD Offset Voltage Common Mode Common-Mode Difference, ΔV OS Short-Circuit Output Current Frequency Range Duty Cycle Rise/Fall Time 1 (20% to 80%) CMOS MODE Output Voltage ...
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AD9552 SERIAL CONTROL PORT Table 5. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input ...
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ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. ...
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AD9552 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic Type 29, 30, 31, Y0, Y1, Y2, Y3, Y4 A0, A1 RESET I 7, 18, ...
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TYPICAL PERFORMANCE CHARACTERISTICS CARRIER 624.988784MHz –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 100 1k 10k 100k FREQUENCY (Hz) Figure 3. Phase Noise, Fractional-N, Pin Programmed (f = 19.44 MHz, f ...
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AD9552 100 150 FREQUENCY (MHz) Figure 9. Supply Current vs. Output Frequency, CMOS (15 pF Load) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 100 200 300 FREQUENCY (MHz) Figure ...
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Figure 15. Typical Output Waveform, LVDS (805 MHz, 3.5 mA Drive Current) Figure 16. Typical Output Waveform, CMOS (250 MHz Load) Rev Page AD9552 1.25ns/DIV ...
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AD9552 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF AD9552 HIGH 3.3V IMPEDANCE DIFFERENTIAL INPUT OUTPUT (LVDS OR 0.1µF LVPECL MODE) Figure 17. AC-Coupled LVDS or LVPECL Output Driver AD9552 3.3V DOWNSTREAM DIFFERENTIAL DEVICE OUTPUT (LVDS OR LVPECL MODE) Rev Page 12 ...
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THEORY OF OPERATION DETECTOR REFA XTAL TUNING CONTROL XTAL 3 SERIAL REGISTER BANK PORT 3 A2:0 PRECONFIGURED 6 DIVIDER VALUES Y5:0 PRESET FREQUENCY RATIOS The frequency selection pins (A[2:0] and Y[5:0]) allow the user to hardwire the device for preset ...
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AD9552 Table 10. Output Frequency Selection Pins ...
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AD9552 The gain of the PLL is proportional to the current delivered by the charge pump. The user can override the default charge pump current setting, and, thereby, the PLL gain, by using Register 0x0A[7:0]. The PLL has a VCO ...
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PART INITIALIZATION AND AUTOMATIC POWER- ON RESET The AD9552 has an internal power-on reset circuit. At power-up, internal logic relies on the internal reference monitor to select either the crystal oscillator or the reference input and then initiates VCO calibration ...
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AD9552 The P and P combinations listed in Table 12 are all equally 0 1 valid. However, note that they yield only three valid ODF values (35, 36, and 40) from the original range 40. 3. Determine ...
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APPLICATIONS INFORMATION THERMAL PERFORMANCE Table 13. Thermal Parameters for the 32-Lead LFCSP Package Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board θ Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) JA θ Junction-to-ambient thermal ...
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AD9552 SERIAL CONTROL PORT The AD9552 serial control port is a flexible, synchronous, serial communications port that allows an easy interface to many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or ...
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By default, a read request reads the register value that is currently in use by the AD9552. However, setting Register 0x04[ causes the buffered registers to be read instead. The buffered registers are the ones that take effect ...
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AD9552 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 24. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data CS ...
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REGISTER MAP A bit that is labeled “aclr” active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns Logic 0 state upon completion of the indicated task. Table 17. ...
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AD9552 Addr. Register (Hex) Name (MSB) Bit 7 Bit 6 0x1C XTAL Unused Unused control 0x1D XTAL Unused Unused control 0x32 OUT1 OUT1 drive OUT1 driver strength power- control down 0x33 Select OUT2 Unused Unused source 0x34 OUT2 OUT2 drive ...
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PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D) Table 19. Address Bit Bit Name 0x0A [7:0] Charge pump current control 0x0B 7 Enable SPI control of charge pump current 6 Enable SPI control of antibacklash period [5:4] ...
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AD9552 VCO Control (Register 0x0E to Register 0x10) Table 20. Address Bit Bit Name 0x0E 7 Calibrate VCO 6 Enable ALC [5:3] ALC threshold 2 Enable SPI control of VCO calibration 1 Boost VCO supply 0 Enable SPI control of ...
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Address Bit Bit Name 0x18 [7:3] P divider 1 [2:0] P divider 0 0x19 7 Enable SPI control of OUT1 dividers [6:0] Unused Input Receiver and Band Gap Control (Register 0x1A) Table 22. Address Bit Bit Name 0x1A 7 Receiver ...
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AD9552 OUT1 Driver Control (Register 0x32) Table 24. Address Bit Bit Name 0x32 7 OUT1 drive strength 6 OUT1 power-down [5:3] OUT1 mode control [2:1] OUT1 CMOS polarity 0 Enable SPI control of OUT1 driver control Select OUT2 Source Control ...
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OUT2 Driver Control (Register 0x34) Table 26. Address Bit Bit Name 0x34 7 OUT2 drive strength 6 OUT2 power-down [5:3] OUT2 mode control [2:1] OUT2 CMOS polarity 0 Enable SPI control of OUT2 driver control Description Controls the output drive ...
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... INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9552BCPZ −40°C to +85°C AD9552BCPZ-REEL7 −40°C to +85°C AD9552/PCBZ RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ 0.50 0.40 17 0.30 ...
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NOTES Rev Page AD9552 ...
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AD9552 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07806-0-7/10(C) Rev Page ...