CDB4382 Cirrus Logic Inc, CDB4382 Datasheet - Page 3

• Manufacturer Part Number: CDB4382
• Description: Development Kit
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4382

• Silicon Manufacturer: Cirrus Logic
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: CS4382
• Kit Contents: Evaluation Board
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CDB4382 SYSTEM OVERVIEW
The CDB4382 evaluation board is an excellent
means of quickly evaluating the CS4382. The
CS8414 digital audio interface receiver provides an
easy interface to digital audio signal sources in-
cluding the majority of digital audio test equip-
ment. The evaluation board also allows the user to
supply either PCM or DSD clocks and data through
headers for system development.
The CDB4382 schematic has been partitioned into
10 schematics shown in Figures 3 through 12. Each
partitioned schematic is represented in the system
diagram shown in Figure 2. Notice that the system
diagram also includes the interconnections be-
tween the partitioned schematics.
1. CS4382 DIGITAL TO ANALOG
A description of the CS4382 is included in the
CS4382 datasheet.
2. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 4. The outputs of the CS8414 in-
clude a serial bit clock, serial data, left-right clock
(FSYNC), and a 256 Fs master clock. The CS8414
data format has been configured for I
ation of the CS8414 and a discussion of the digital
audio interface is included in the CS8414
datasheet.
The evaluation board has been designed such that
the input can be either optical or coax, see Figure 4.
However, both inputs cannot be driven simulta-
neously.
3. INPUT/OUTPUT FOR CLOCKS AND
The evaluation board has been designed to allow
interfacing to external systems via the 18-pin head-
ers, J15 and J16. Header J15 allows the evaluation
board to accept externally generated PCM clocks
CONVERTER
DATA
2
S. The oper-
and data. The schematic for the clock/data input is
shown in Figure 5.
Header J16 allows the evaluation board to accept
externally generated DSD data and clock. The
schematic for the clock/data input is shown in
Figure 6. A synchronous MCLK must still be pro-
vided via header J15. Please see the CS4382
datasheet for more information.
4. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by seven
binding posts (GND, +5V, VLS, VLC, VD, +18V
and -18V), see Figure 12. The VLC and VLS sup-
plies can be jumpered to the +5V binding post for
ease of use. VD and VA should be set to the recom-
mended values stated in the CS4382 datasheet.
+18V and -18V supply power to the op-amps and
can be +/-5 to +/-18 volts (must be +/-18 V when
filter 2 is selected).
WARNING: Refer to the CS4382 datasheet for
maximum allowable voltages levels. Operation
outside of this range can cause permanent damage
to the device.
5. GROUNDING AND POWER SUPPLY
The CS4382 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 3 details the connections to
the CS4382 and Figures 13 & 14, 15 show the com-
ponent placement and top and bottom layout. The
decoupling capacitors are located as close to the
CS4382 as possible. Extensive use of ground plane
fill in the evaluation board yields large reductions
in radiated noise.
6. CONTROL PORT SOFTWARE
The CDB4382 is shipped with Windows 95/98/ME
based software for interfacing with the CS4382
control port via the DB25 connector, J1 (Windows
NT and 2000 not currently supported). The soft-
ware can be used to communicate with the CS4382
DECOUPLING
CDB4382
3