SC4521EVB-2 Semtech, SC4521EVB-2 Datasheet - Page 9

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SC4521EVB-2

Manufacturer Part Number
SC4521EVB-2
Description
EVALUATION BOARD
Manufacturer
Semtech
Datasheet

Specifications of SC4521EVB-2

Silicon Manufacturer
Semtech
Application Sub Type
Step Down Switching Regulator
Kit Application Type
Power Management - Voltage Regulator
Silicon Core Number
SC4521
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Thermal Considerations
There are three major power dissipation sources for the
SC4521. The internal switch conduction loss, its switching
loss due to the high frequency switching actions and the
base drive boost circuit loss. These losses can be
estimated as:
Where:
I
R
V
connection.
The junction temperature of the SC4521 can be
further determined by:
Its value is a function of the IC package, the application
layout and the air cooling system.
The freewheeling diode also contributes a significant
portion of the total converter loss. This loss should be
minimized to increase the converter efficiency by using
Schottky diodes with low forward drop (V
Loop Compensation Design
The SC4521 has an internal error amplifier and requires
a compensation network to connect between the COMP
pin and GND pin as shown in Figure 3. The compensation
network includes C4, C5 and R3. R1 and R2 are used to
program the output voltage according to:
Assuming the power stage ESR (equivalent series
resistance) zero is an order of magnitude higher than
the closed loop bandwidth, which is typically one tenth of
the switching frequency, the power stage control to output
transfer function with the current loop closed (Ridley
model) for the SC4521 will be as follows:
POWER MANAGEMENT
Application Information (Cont.)
O
BOOST
on
2007 Semtech Corp.
JA
P
= load current;
total
= on-equivalent resistance of the switch;
is the thermal resistance from junction to ambient.
= input voltage or output based on the boost circuit
I
o
2
R
on
D
P
T
diode
J
10.8
G
V
T
VD
O
A
(s)
V
10
F
0
θ
8 .
JA
I
o
3
1
(1
4.3
1 (
P
I
o
total
R
D)
L
V
R
R
R
s
1
I
2
1
L
C
)
1000
10
F
).
I
o
D
(V
boost
)
9
Where:
R
C – Output capacitor.
The goal of the compensation design is to shape the loop
to have a high DC gain, high bandwidth, enough phase
margin, and high attenuation for high frequency noises.
Figure 3 gives a typical compensation network which
offers 2 poles and 1 zero to the power stage:
Figure 3. Compensation network provides 2 poles and
1 zero.
The compensation network gives the following
characteristics:
Where:
The loop gain will be given by:
Where:
T(s)
L
– Load and
2
2
5
5
8
8
G
COMP
EN
EN
IN
IN
SS
SS
(s)
G
G
COMP
SC4521
SC4521
COMP
COMP
VD
FB
FB
SW
SW
(s)
(s)
3
3
6
6
7
7
C5
C5
3.655
ω
ω
P2
1
ω
ω
ω
1
Z
s
p1
10
R
1
(1
C
R3
R3
C
R
3
3
C4
C4
R
4
4
3
ω
R
C
C
L
1
ω
1
s
1
Z
L
4
s
C
4
C
P2
C
C
4
5
5
C
R
)
5
1
R
D2
D2
g
2
m
R
2
L1
L1
R
1
1
s
R
(1
www.semtech.com
SC4521
R2
R2
R1
R1
2
R
2
ω
s
1
P1
C
C
)
ω
(1
s
Z
ω
Vout
Vout
s
P2
)

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