AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet
AD9553/PCBZ
Specifications of AD9553/PCBZ
Related parts for AD9553/PCBZ
AD9553/PCBZ Summary of contents
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FEATURES Input frequencies from 8 kHz to 710 MHz Output frequencies up to 810 MHz LVPECL and LVDS (up to 200 MHz for CMOS output) Preset pin-programmable frequency translation ratios cover popular wireline and wireless frequency applications, including xDSL, T1/E1, ...
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AD9553 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Basic Block Diagram ........................................................................ 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Power Consumption .................................................................... 3 Logic Input Pins ............................................................................ 3 Logic Output Pins ......................................................................... 3 ...
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SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD = 3 25°C, unless otherwise noted. A POWER CONSUMPTION Table 1. Parameter ...
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AD9553 RESET PIN Table 4. Parameter 1 INPUT CHARACTERISTICS Input Voltage High Input Voltage Low Input Current High, I INH Input Current Low, I INL MINIMUM PULSE WIDTH LOW The RESET pin has a 100 kΩ ...
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VCO CHARACTERISTICS Table 6. Parameter FREQUENCY RANGE VCO GAIN VCO TRACKING RANGE VCO CALIBRATION TIME Low Bandwidth Setting (170 Hz) 13.3 kHz PFD Frequency 16 kHz PFD Frequency Medium Bandwidth Setting (20 kHz) 1.5625 MHz PFD Frequency High Bandwidth Setting ...
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AD9553 OUTPUT CHARACTERISTICS Table 8. Parameter LVPECL MODE Differential Output Voltage Swing Common-Mode Output Voltage Frequency Range Duty Cycle 1 Rise/Fall Time (20% to 80%) LVDS MODE Differential Output Voltage Swing Balanced Unbalanced, ΔV OD Offset Voltage Common ...
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JITTER CHARACTERISTICS Table 9. Parameter Min JITTER GENERATION 12 kHz to 20 MHz LVPECL Output LVDS Output CMOS Output 50 kHz to 80 MHz LVPECL Output LVDS Output CMOS Output JITTER TRANSFER BANDWIDTH Low Bandwidth Setting Medium Bandwidth Setting High ...
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AD9553 SERIAL CONTROL PORT Table 10. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input ...
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ABSOLUTE MAXIMUM RATINGS Table 12. Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the ...
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AD9553 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 13. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 29, 30, 31, Y0, Y1, Y2, Y3, I Control Pins. These pins select one of 52 preset output frequency combinations for OUT1 and ...
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TYPICAL PERFORMANCE CHARACTERISTICS –30 JITTER BANDWIDTH –40 12kHz TO 20MHz 50kHz TO 80MHz –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY OFFSET FROM CARRIER (Hz) Figure 3. Phase Noise, Pin ...
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AD9553 5 0 –5 2 –10 1 JITTER PEAKING –15 0 –1 –20 –2 –25 – 100 125 150 175 FREQUENCY OFFSET (Hz) –30 10 100 FREQUENCY OFFSET (Hz) Figure 9. Jitter Transfer, Loop Bandwidth = ...
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LVPECL 30 LVDS STRONG 25 20 LVDS WEAK 100 200 300 400 500 600 700 FREQUENCY (MHz) Figure 15. Supply Current vs. Output Frequency, LVPECL and LVDS (10 pF Load) 30 20pF 25 10pF ...
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AD9553 2 200mV/DIV Figure 21. Typical Output Waveform, LVPECL (800 MHz) 2 125mV/DIV Figure 22. Typical Output Waveform, LVDS (800 MHz, 3.5 mA Drive Current) 2 500ps/DIV 500ps/DIV Rev Page 500mV/DIV 1.25ns/DIV Figure 23. Typical ...
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INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF AD9553 HIGH IMPEDANCE 3.3V DIFFERENTIAL INPUT OUTPUT (LVDS OR 0.1µF LVPECL MODE) Figure 24. AC-Coupled LVDS or LVPECL Output Driver AD9553 3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE) Figure 25. DC-Coupled LVDS or LVPECL Output Driver ...
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AD9553 THEORY OF OPERATION REFERENCE CLOCK MUX SWITCHOVER SEL REFB CONTROL HOLD REF DET DET DET SEL REFA ÷5 REF ÷5 A DIFF REFB/REFA 0 1 ÷5 ÷ XTAL DCXO TUNING ...
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The Ax pins allow the user to select one of fifteen input reference frequencies as shown in Table 14. The device sets the appropriate divide-by-5 (÷5 , ÷5 ), multiply-by-2 (× divider ( ...
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AD9553 Table 15. Pin Configured Output Frequency, Yx Pins Pin Y5 to Pin Y0 f (MHz) VCO 000000 000001 3686.4 000010 3686.4 000011 3686.4 000100 3686.4 000101 3686.4 000110 3686.4 000111 3686.4 001000 3686.4 001001 3686.4 001010 3686.4 001011 3686.4 ...
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Table 16. Pin Configuration vs. PLL Feedback Divider (N) and Charge Pump Value (CP 0001 to 1100 1101 1110 1111 1 PLL feedback divider value (decimal). 2 Charge pump register value (decimal). Multiply by 3.5 µA to ...
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AD9553 SPI/OM[2:0] SPI CONTROLLER OUTPUT MODE CONTROL FUNCTION BITS FUNCTION ABC BITS FUNCTION XYZ BITS REGISTER MAP Although the SPI and pin control modes are functionally independent possible to mix the control modes. For example, suppose that pin ...
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After applying power to the AD9553 (or after a device reset), the programmable component defaults to 2 pF. This establishes the default ...
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AD9553 R DIVIDER A FROM REFA ÷ INPUT R DIVIDER B FROM REFB ÷ INPUT R DIVIDER XO FROM XTAL ÷ INPUT SIGNAL FDBK DETECTOR REG 0x29[7:6] REVERTIVE 00 NON-REVERTIVE 01 SELECT REFA 10 SELECT REFB 11 The user can ...
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Loop Filter The charge pump in the PFD delivers current to the loop filter (see Figure 30). The components primarily responsible for the bandwidth of the loop filter are external and connect between Pin 16 and Pin 17. The internal ...
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AD9553 The mode control bits establish the logic family and output pin function of the associated output driver per Table 19. The logic families include LVDS, LVPECL, and CMOS. Because both output drivers support the LVDS and LVPECL logic families, ...
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OM[2:0] Output Driver Polarity (CMOS) When the mode control bits indicate the CMOS logic family (see Table 19), the user has control of the logic polarity asso- ciated with each CMOS output pin. Driver polarity defines how the logic level ...
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AD9553 JITTER TOLERANCE Jitter tolerance is the ability of the AD9553 to maintain lock in the presence of sinusoidal jitter. The AD9553 meets the input jitter tolerance mask per Telcordia GR-253-CORE (see Figure 32). The acceptable jitter tolerance is the ...
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Generally, the AD9553 is for applications in which f are the same frequency, so the multiplexers in the REFA and REFB paths share identical configurations. This, in conjunction with the crystal frequency (f ), results in the following rela- XTAL ...
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AD9553 5. Determine N, K, and R. For f = 3888 MHz, an obvious solution 125, VCO and N = 3888, which satisfies the constraint on both N and R, and yields FPFD = ...
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APPLICATIONS INFORMATION THERMAL PERFORMANCE The AD9553 is specified for case temperature (T that T is not exceeded, use an airflow source. Use the following CASE equation to determine the junction temperature on the applica- tion printed circuit board (PCB): T ...
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AD9553 SERIAL CONTROL PORT The AD9553 serial control port is a flexible, synchronous, serial communications port that allows an easy interface to many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or ...
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By default, a read request reads the register value that is currently in use by the AD9553. However, setting Register 0x04[ causes the buffered registers to be read instead. The buffered registers are the ones that take effect ...
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AD9553 CS SCLK DON'T CARE SDIO DON'T CARE R A12 A11 A10 16-BIT INSTRUCTION HEADER Figure 36. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data CS ...
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REGISTER MAP A bit that is labeled ACLR is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns Logic 0 state upon completion of the indicated task. Table 27. ...
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AD9553 Addr. Register (MSB) (Hex) Name Bit 7 Bit 6 0x1F REFA frequency 0x20 control 0x21 Enable SPI Select × control 0x22 Unused Unused Unused 0x23 REFB frequency 0x24 control 0x25 Enable SPI Select control of × ...
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REGISTER MAP DESCRIPTIONS Control bit functions are active high unless stated otherwise. Register address values are always hexadecimal unless otherwise indicated. Serial Port Control (Register 0x00 to Register 0x05) Table 28. Address Bit Bit Name 0x00 7 Unused 6 LSB ...
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AD9553 Address Bit Bit Name 0x0C [7:3] Unused [2:0] Charge pump clock div. 0x0D [7:6] Antibacklash control [5:1] Unused 0 PLL lock detector power-down VCO Control (Register 0x0E to Register 0x10) Table 30. Address Bit Bit Name 0x0E 7 Calibrate ...
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PLL and Output Frequency Control (Register 0x11 to Register 0x19) Table 31. Address Bit Bit Name 0x11 [7:0] Unused 0x12 [7:0] Feedback divider (N) 0x13 [7:0] Feedback divider (N) 0x14 [7:4] Feedback divider (N) 3 Enable SPI control of feedback ...
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AD9553 Input Receiver and Band Gap Control (Register 0x1A) Table 32. Address Bit Bit Name 0x1A 7 Receiver reset [6:2] Band gap voltage adjust 1 Unused 0 Enable SPI control of band gap voltage XTAL Control (Register 0x1B to Register ...
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REFB Frequency Control (Register 0x23 to Register 0x26) Table 35. Address Bit Bit Name 0x23 [7:0] REFB divider ( 0x24 [7:2] REFB divider ( Enable SPI control Unused 0x25 7 Enable SPI ...
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AD9553 OUT1 Driver Control (Register 0x32) Table 37. Address Bit Bit Name 0x32 7 OUT1 drive strength 6 OUT1 power-down [5:3] OUT1 mode control 2 OUT1 CMOS polarity 1 Unused 0 OUT1 mode source Reserved (Register 0x33) Table 38. Address ...
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OUT2 Driver Control (Register 0x34) Table 39. Address Bit Bit Name 0x34 7 OUT2 drive strength 6 OUT2 power-down [5:3] OUT2 mode control 2 OUT2 CMOS polarity 1 Unused 0 OUT1 mode source Description Controls the output drive capability of ...
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... AD9553 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9553BCPZ −40°C to +85°C AD9553BCPZ-REEL7 −40°C to +85°C AD9553/PCBZ RoHS Compliant Part. 5.10 0.30 5.00 SQ 0.25 4.90 0. 0.50 BSC 17 16 0.50 TOP VIEW BOTTOM VIEW ...
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NOTES Rev Page AD9553 ...
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AD9553 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08565-0-10/10(A) Rev Page ...