HW-USB-IIG Xilinx Inc, HW-USB-IIG Datasheet
HW-USB-IIG
Specifications of HW-USB-IIG
Related parts for HW-USB-IIG
HW-USB-IIG Summary of contents
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... Directly programs selected Serial Peripheral Interface (SPI) flash memory devices • Indirectly programs selected SPI or parallel flash memory devices via FPGA JTAG port • Highly optimized for use with Xilinx design tools • ISE® Foundation™ Software • Embedded Development Kit • ...
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... In addition, Platform Cable USB II is optimized for use with Xilinx Embedded Development Kit, ChipScope Pro Analyzer and System Generator for DSP. When used with these software tools, the cable provides a connection to embedded target systems for hardware configuration, software download, and real-time debug and verification. Target clock speeds are selectable from 750 kHz to 24 MHz ...
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... Platform Cable USB II is designed to take full advantage of the bandwidth of USB 2.0 ports, but it is also backward- compatible with USB 1.1 ports. Refer to connection environments and bandwidth. Table 1 lists Platform Cable USB II compatibility with the Xilinx design tools. DS593 (v1.2.1) March 17, 2011 ® Platform Cable USB II ...
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... Xilinx design tool is installed. Note: Automatic driver installation is available beginning with version 10.1 of Xilinx design tools. For earlier versions, a driver installer must be run prior to using the cable. Refer to the USB Cable Installation Guide for instructions on downloading and running the installer. Firmware Updates The Platform Cable USB II firmware resides in an USB microcontroller and a FPGA/PROM ...
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... Connecting to the Cable in iMPACT This section describes some of the ways to connect to Platform Cable USB II using the Xilinx iMPACT graphical user interface (GUI). For cable communication using other Xilinx design tools or methods, please refer to the appropriate software user guide. Select a Flow From the iMPACT GUI, select a flow on the “ ...
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X-Ref Target - Figure 4 Option 2: Manual Cable Connect To manually connect the cable, select Output → Cable Setup. Select the Xilinx USB Cable radio button in the Cable Communication Setup dialog box (Figure X-Ref Target - Figure 5 ...
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... GUI immediately indicates "No Cable Connection." Xilinx design tools employ system semaphores to manage access to Xilinx cables, allowing multiple applications to simultaneously access (connect to) a single cable (but only one application can perform cable operations at a given time). ...
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... BSDL file for maximum JTAG TCK specifications. Note: Certain Xilinx design tools and iMPACT versions earlier than 7.1i do not restrict the TCK_CCLK_SCK selections in JTAG mode. Accordingly, users should take care to select a TCK_CCLK_SCK frequency matching the JTAG TCK specifications for the slowest device in the target chain ...
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Cable Status Bar A status bar on the bottom edge of the iMPACT GUI example, if the host port is USB 2.0, Platform Cable USB II connects at Hi-Speed and the status bar shows usb-hs. If the host port ...
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The status LED is off whenever Platform Cable USB II enters a suspend state (see disconnected from a USB port connected to an un-powered USB port. Table 4 summarizes the various status LED states. Table 4: Interpreting the ...
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... A 6-inch ribbon cable is supplied and recommended for connection to target systems multiple signal-ground pairs and facilitates error-free connections. The Xilinx product number for the 6-inch ribbon cable is HW-RIBBON14. To take advantage of the ribbon cable, a mating connector must be incorporated into the target system. This connector is normally installed only during prototype checkout ...
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... Note: This method of connection is not recommended because it can result in poor signal integrity. Additionally, damage can result if the leads are unintentionally connected to high voltages. The Xilinx product number for the flying wire set is HW-USB-FLYLEADS-G. X-Ref Target - Figure 11 Platform Cable USB II Model DLC10 Power 5V 0 ...
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X-Ref Target - Figure 12 Figure 12: Flying Wire Adapter (Side) without Wires Physical Connection to the Host Each Platform Cable USB II includes a detachable, Hi-Speed-USB-certified, 1.8-meter A–B cable circumstances should user-supplied cables exceed 5 meters. Sub-channel cables (intended ...
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Target Interface Connectors Mating connectors for attachment of the high-performance ribbon cable to a target system are available in both through-hole and surface mount configurations (Figure orientation when inserting the cable. The connector requires only 105 mm The target system ...
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... A similar scheme can be used with Slave Serial topologies. PGND control is available only in iMPACT versions 10.1 and later. PGND remains high-Z in earlier versions of iMPACT and in Xilinx design tools where the PGND signal is not supported. The DONE pin on FPGAs can be programmed open-drain or active driver. For cascaded Slave Serial topologies, an external pull-up resistor should be used, and all devices should be programmed for open-drain operation ...
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X-Ref Target - Figure 16 V TDO TDI TMS TCK (1) V CCAUX 2-mm Connector 2 V REF 8 TDO 10 TDI TMS 4 6 TCK (5) 13 PGND (2) * GND Notes: 1. Example implies that ...
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Direct SPI Platform Cable USB II can connect directly to a single SPI flash device. connection. XAPP951, Configuring Xilinx FPGAs with SPI Serial Flash provides additional details of the cable connections necessary to program a FPGA bitstream into a SPI ...
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... XAPP974, Indirect Programming of SPI Serial Flash PROMs with Spartan-3A FPGAs. Indirect BPI When used with Xilinx design tools, Platform Cable USB II can be used to indirectly program Platform Flash XL, or some third-party NOR flash memories (BPI PROMs) via the target FPGA's JTAG port. For a description of the indirect Platform Flash programming solution, see UG438, Platform Flash XL User Guide ...
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... The output drivers are enabled only during cable operations; otherwise, they are set to high-Z between operations. Xilinx design tools actively drive the outputs to logic 1 before setting the respective buffer to high-Z, avoiding the possibility of a slow rise-time transition caused by a charge path through the pull-up resistor into parasitic capacitance on the target system ...
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X-Ref Target - Figure 19 X-Ref Target - Figure 20 FPGA Output High-Z Control DS593 (v1.2.1) March 17, 2011 Figure 19: V Current vs. V REF REF V NC7SZ126 REF_CLAMP 30.1Ω BAT54 To input buffer Figure 20: Target Interface Driver ...
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X-Ref Target - Figure 21 Input Receive Structure Each input signal is routed through a NC7WZ07 ultra high-speed CMOS, open-drain receive buffer. Series-termination resistors (499Ω) provide current limit protection for positive and negative excursions. Schottky diodes provide the input buffers ...
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... Slave Serial or SPI modes. Note: HALT signal control is available in iMPACT 9.2i and later. HALT remains high-Z in earlier versions of iMPACT and in Xilinx design tools where the HALT signal is not supported. DS593 (v1.2.1) March 17, 2011 NC7WZ07 ...
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X-Ref Target - Figure 24 Figure 24: Enabling the HALT Signal in iMPACT (9.2i) Timing Specifications For JTAG, SPI, and Slave Serial configuration modes, the TDI_DIN_MOSI and TMS_PROG_SS outputs change on falling edges of TCK_CCLK_SCK (Figure TCK_CCLK_SCK. The minimum setup ...
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Note: The propagation delay from TCK to TDO is 26 ns. Because is attributable exclusively to input delays in the cable MHz, there is still sufficient setup time before the cable samples prior to the next negative TCK ...
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X-Ref Target - Figure 26 Figure 26: TDO Sampling Example at 12 MHz (TDO Propagation Delay) DS593 (v1.2.1) March 17, 2011 Negative TCK transition at G1 causes target device to change TDO state, which propagates to the cable at G2 ...
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X-Ref Target - Figure 27 TDO setup time prior to internal sampling clock (G2 – G1) is 42ns in this 12-MHz example. Figure 27: TDO Sampling Example at 12 MHz (TDO Setup Time Relative to Sampling Point) DS593 (v1.2.1) March ...
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X-Ref Target - Figure 28 Propagation delay from (26 ns) captured directly at the target represents 70% of the total propagation delay seen by the cable (Figure 25). TCK TDO Figure 28: TDO Sampling Example at 12 ...
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Each differential receiver can drive multiple target devices if there are no branches on the PCB trace and the total trace length is less than four inches. A series termination resistor should be placed adjacent to the single-ended output of ...
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X-Ref Target - Figure 30 (A) 12 Mb/s Bus Speed 12 Mb/s Bus Speed 1.X Root Hub 1.X Root Hub 500 mA 2.0 External Platform Cable Bus-Powered USB II Enumerates at full speed because root hub only operates at full ...
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Table 6: JTAG/SPI/Slave Serial Port: 2-mm Connector Signals (Cont’d) MODE Pin JTAG Number Configuration Programming 10 TDI 13 PGND 14 HALT 4 – 6 – 8 – 10 – 13 – PGND 14 – 4 – 6 – DS593 (v1.2.1) ...
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Table 6: JTAG/SPI/Slave Serial Port: 2-mm Connector Signals (Cont’d) MODE Pin JTAG Number Configuration Programming 8 – 10 – 13 – 14 – – – Notes: 1. The listed SPI pin names match ...
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Table 7: Absolute Maximum Ratings Symbol Description DC Output Current (TCK_CCLK_SCK, I OUT TMS_PROG_SS, TDI_DIN_MOSI, and INIT) Notes: 1. Exposure to absolute rating conditions for extended periods of time can affect product reliability. The values listed in this table are ...
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Table 10: Switching Characteristics Symbol Description T Target Setup Time TSU (TDI or TMS relative to the positive edge of TCK) T Cable Setup Time CSU (TDO relative to the negative edge of TCK) T Target Propagation Delay Time TPD ...
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... Ribbon Cable, 6-inch Flying Wire Set HW-USB-FLYLEADS-G Marking Information Table 12: Marking Information Model Name Serial Prefix DLC10 XU DS593 (v1.2.1) March 17, 2011 Table 11 plus a 1.8-meter, Hi-Speed USB, A-B cable. Product Number HW-USB-II-G HW-RIBBON14 Description Platform Cable USB II www.xilinx.com Platform Cable USB II 34 ...
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Revision History The following table shows the revision history for this document: Date Version 03/03/08 1.0 Initial Xilinx release. 05/14/08 1.1 • Updated trademark references. • Added support for Platform Flash XL. 06/09/08 1.2 Corrected the functional descriptions of pins ...