WM8524-6228-DT16-EV1 Wolfson Microelectronics, WM8524-6228-DT16-EV1 Datasheet
WM8524-6228-DT16-EV1
Specifications of WM8524-6228-DT16-EV1
Related parts for WM8524-6228-DT16-EV1
WM8524-6228-DT16-EV1 Summary of contents
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... Stereo DAC with 2Vrms Ground Referenced Line Output DESCRIPTION The WM8524 is a stereo DAC with integral charge pump and hardware control interface. This provides 2Vrms line driver outputs using a single 3.3V power supply rail. The device features ground-referenced outputs and the use ...
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... WM8524 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ......................................................................... 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ...................................................................... 6 TERMINOLOGY ............................................................................................................ 6 POWER CONSUMPTION MEASUREMENTS .............................................................. 7 SIGNAL TIMING REQUIREMENTS ....................................................................... 8 SYSTEM CLOCK TIMING ............................................................................................. 8 AUDIO INTERFACE TIMING – SLAVE MODE .............................................................. 9 POWER ON RESET CIRCUIT .................................................................................... 10 DEVICE DESCRIPTION ...
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... Note: Reel quantity = 2000 w LINEVOUTR AVDD VMID AGND AIFMODE MUTE MCLK BCLK PACKAGE MOISTURE SENSITIVITY LEVEL 16 lead TSSOP (Pb-free) 16-lead TSSOP (Pb-free, tape and reel) WM8524 PEAK SOLDERING TEMPERATURE o MSL1 260 C o MSL1 260 C PD, Rev 4.0, June 2010 3 ...
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... WM8524 PIN DESCRIPTION PIN NO NAME TYPE 1 Analogue Out LINEVOUTL Analogue Out 2 CPVOUTN 3 Analogue Out CPCB 4 Supply LINEGND 5 Analogue Out CPCA 6 Supply LINEVDD 7 Digital In DACDAT Digital In 8 LRCLK 9 Digital In BCLK 10 Digital In MCLK 11 Digital In MUTE ¯ ¯ ¯ ¯ ¯ Digital In 12 AIFMODE ...
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... TEST CONDITIONS It is therefore generically Proper ESD precautions must be taken during MIN MAX -0.3V +4.5V LINEGND -0.3V LINEVDD +0.3V AGND -0.3V AVDD +0.3V -40°C +125°C -65°C +150°C MIN TYP MAX 2.97 3.3 3.63 0 PD, Rev 4.0, June 2010 WM8524 UNIT ...
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... WM8524 ELECTRICAL CHARACTERISTICS Test Conditions LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, T stated. PARAMETER Analogue Output Levels Output Level Load Impedance Load Capacitance DAC Performance Signal to Noise Ratio Dynamic Range Total Harmonic Distortion AVDD + LINEVDD Power Supply Rejection Ratio Channel Separation System Absolute Phase Channel Level Matching ...
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... MUTE ¯ ¯ ¯ ¯ ¯ 0.2 ¯ ¯ ¯ ¯ ¯ MUTE 5.5 ¯ ¯ ¯ ¯ ¯ MUTE 0.2 ¯ ¯ ¯ ¯ ¯ MUTE 5.5 WM8524 ILINEVDD TOTAL (mA) (mA) 1.1 1.9 2.2 2.4 6.0 10.8 2.9 3.1 8 ...
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... WM8524 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T PARAMETER Master Clock Timing Information MCLK cycle time MCLK high time MCLK low time MCLK duty cycle (t /t MCLKH MCLKL) w =+25°C A SYMBOL MIN TYP ...
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... DACDAT set-up time to BCLK rising edge Table 1 Slave Mode Audio Interface Timing Note: BCLK period should always be greater than or equal to MCLK period BCY t BCL t t LRH LRSU ° =+25 C, Slave Mode A SYMBOL t BCY t BCH t BCL t LRSU t LRH WM8524 MIN TYP MAX UNIT PD, Rev 4.0, June 2010 9 ...
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... POWER ON RESET CIRCUIT Figure 3 Internal Power on Reset Circuit Schematic The WM8524 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is used to reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a minimum threshold ...
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... Table 2 Power on Reset Note: All values are simulated results + TEST CONDITIONS V Measured from LINEGND pora Measured from LINEGND pord_hi Measured from LINEGND pora_hi Measured from LINEGND pora_lo WM8524 MIN TYP MAX UNIT 158 mV 0.63 0 1.44 1.8 2.18 V 0.96 1.46 1.97 V PD, Rev 4 ...
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... The WM8524 supports a simple hardware control mode, allowing access to 24-bit LJ, RJ and I2S audio interface formats, as well as a mute control. automatically mutes the DAC output if the BCLK is interrupted. DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting audio data to the WM8524. The digital audio interface uses three pins: • • ...
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... The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. w All other bits are transmitted before (MSB first). Depending on word length, BCLK WM8524 PD, Rev 4.0, June 2010 13 ...
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... Power up and down control section of the datasheet on page 16. The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz. Table 3 shows typical master clock frequencies and sampling rates supported by the WM8524 DAC. Sampling Rate LRCLK ...
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... DAC mute to both left and right channels. When the mute is asserted a softmute is applied to ramp the signal down in 800 samples. When the mute is de-asserted the signal returns to full scale in one step. w PIN DESCRIPTION NUMBER 11 Mute Control 0 = Mute 1 = Normal operation 12 Audio Interface Mode 0 = 24-bit 24-bit 24-bit RJ WM8524 PD, Rev 4.0, June 2010 15 ...
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... WM8524 POWER UP AND DOWN CONTROL The MCLK, BCLK and MUTE this is summarised in Figure 9 below. Figure 9 Hardware Power Sequence Diagram Off to Enable To power up the device to enabled, start MCLK and BCLK and set MUTE Off to Standby To power up the device to standby, start MCLK and BCLK and set MUTE device is in standby mode, BCLK can be disabled and the device will remain in standby mode ...
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... Table 5 Power Domains w BLOCKS USING DOMAIN DESCRIPTION THIS DOMAIN Line Driver Analogue Supply DAC DC Servo Charge Pump Analogue Supply Digital LDO Digital Pad buffers DAC, LDO Ext decoupled resistor string Line Driver Charge pump generated voltage WM8524 PD, Rev 4.0, June 2010 17 ...
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... WM8524 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS DAC Filter – 256fs to 1152fs ± 0.1dB Passband Passband Ripple Stopband Stopband attenuation f > 0.546fs Group Delay DAC Filter – 128fs and 192fs Passband ± 0.1dB Passband Ripple Stopband Stopband attenuation f > 0.753fs Group Delay TERMINOLOGY 1 ...
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... Figure 14 DAC Digital Filter Ripple – 128fs to 192fs Clock Modes 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) DAC Digital Filter Ripple – 256fs to 1152fs 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) PD, Rev 4.0, June 2010 WM8524 0.45 0.5 0.45 0.5 19 ...
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... Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimize split ground configuration for audio performance. 2. Charge Pump fly-back capacitor C5 should be placed as close to WM8524 as possible, followed by Charge Pump decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. See Recommended PCB Layout on p21. 3. ...
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... C5 should be placed as close to WM8524 as possible, with minimal track lengths to reduce inductance and maximise performance of the charge pump. Vias should be avoided in the tracking to C5 then next most important and should also be placed as close as possible to the WM8524. Again, minimise track lengths and avoid vias to reduce parasitic inductance. 3. ...
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... The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for use of the WM8524. DEVICE PERFORMANCE: WTN0302 – WM8524 Recommended Power Sequence and Timing WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies GENERAL: WAN0108 – ...
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... C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS GAUGE PLANE 8 -C- 0.1 C SEATING PLANE MAX ----- 1.20 ----- 0.15 1.05 ----- 0.30 ----- 0.20 5.10 4.50 0.75 o ----- 8 WM8524 DM013.B θ 0. PD, Rev 4.0, June 2010 23 ...
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... WM8524 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...