XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet

no-image

XC3S400-4FT256C

Manufacturer Part Number
XC3S400-4FT256C
Description
SEMI CONDUCTOR
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC3S400-4FT256C

Case
BGA
Dc
04+

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S400-4FT256C
Manufacturer:
ISSI
Quantity:
101
Part Number:
XC3S400-4FT256C
Manufacturer:
XILINX
0
Part Number:
XC3S400-4FT256C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC3S400-4FT256C0985
Manufacturer:
XILINX
Quantity:
6 633
Part Number:
XC3S400-4FT256CES
Manufacturer:
XILINX
0
DS099 May 25, 2007
This document includes all four modules of the Spartan™-3 FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS099-1 (v2.2) May 25, 2007
Module 2:
Functional Description
DS099-2 (v2.2) May 25, 2007
IMPORTANT NOTE: Each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation
in this volume.
DS099 May 25, 2007
Product Specification
© 2003-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Introduction
Features
Architectural Overview
Array Sizes and Resources
User I/O Chart
Ordering Information
Input/Output Blocks (IOBs)
-
-
Configurable Logic Blocks (CLBs)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
IOB Overview
SelectIO™ I/O Standards
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
0
Spartan-3 FPGA Family:
Complete Data Sheet
Product Specification
Module 3:
DC and Switching Characteristics
DS099-3 (v2.2) May 25, 2007
Module 4:
Pinout Descriptions
DS099-4 (v2.2) May 25, 2007
DC Electrical Characteristics
-
-
-
-
Switching Characteristics
-
-
-
-
Pin Descriptions
-
Package Overview
Pinout Tables
-
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
DC Characteristics
I/O Timing
Internal Logic Timing
DCM Timing
Configuration and JTAG Timing
Pin Behavior During Configuration
Footprints
1

Related parts for XC3S400-4FT256C

XC3S400-4FT256C Summary of contents

Page 1

R DS099 May 25, 2007 This document includes all four modules of the Spartan™-3 FPGA data sheet. Module 1: Introduction and Ordering Information DS099-1 (v2.2) May 25, 2007 • Introduction • Features • Architectural Overview • Array Sizes and Resources ...

Page 2

R DS099 May 25, 2007 Product Specification ...

Page 3

... XC3S1000 1M 17,280 48 XC3S1500 1.5M 29,952 64 XC3S2000 2M 46,080 80 XC3S4000 4M 62,208 96 XC3S5000 5M 74,880 104 Notes: 1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" Logic Cells/CLB x 1.125 effectiveness. 2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family. ...

Page 4

... Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Notes: 1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices are shown with dashed lines. The XC3S50 has only the block RAM column on the far left • ...

Page 5

R Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configura- tion latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a ...

Page 6

... XC3S400 - - - - XC3S1000 - - - - XC3S1500 - - - - XC3S2000 - - - - XC3S4000 - - - - XC3S5000 - - - - Notes: 1. All device options listed in a given package column are pin-compatible. 2. User = Single-ended user I/O pins. Diff = Differential I/O pairs Available User I/Os and Differential (Diff) I/O Pairs by Package Type FG320 TQ144 PQ208 FT256 ...

Page 7

... Figure 4 Device Type Speed Grade Temperature Range Figure 2: Spartan-3 QFP Package Marking Example for Part Number XC3S400-4PQ208C Temperature Range Figure 3: Spartan-3 BGA Package Marking Example for Part Number XC3S1000-4FT256C Figure 4: Spartan-3 CP132 and CPG132 Package Marking Example for XC3S50-4CP132C DS099-1 (v2.2) May 25, 2007 ...

Page 8

... Device Speed Grade XC3S50 -4 Standard Performance 1 XC3S200 -5 High Performance XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range XC3S50 -4 PQ 208 C Temperature Range Commercial ( Industrial (T Number of Pins : "Implementation and Solder Reflow Guidelines for Pb-Free ...

Page 9

... Added the FG320 package. 07/13/04 1.3 Added information on Pb-free packaging options. 01/17/05 1.4 Referenced Spartan-3 XA Automotive FPGA families in XC3S2000FG456, XC3S4000FG676 options to mask revision code, fabrication facility code, and process technology code. 08/19/05 1.5 Added package markings for BGA packages (Figure 04/03/06 2 ...

Page 10

Spartan-3 FPGA Family: Introduction and Ordering Information 10 10 www.xilinx.com R DS099-1 (v2.2) May 25, 2007 Product Specification ...

Page 11

... Distributed RAM - SRL16 Shift Registers - Carry and Arithmetic Logic - I/O Resources - Embedded Multiplier Blocks - Programmable Interconnect ™ - ISE Design Tools - IP Cores - Embedded Processing and Control Solutions - Pin Types and Package Overview - Package Drawings - Powering FPGAs • UG332: Spartan-3 Generation Configuration User Guide http://www ...

Page 12

Spartan-3 FPGA Family: Functional Description IOBs For additional information, refer to the “Using I/O Resources” chapter in UG331. IOB Overview The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal logic. A simplified ...

Page 13

TCE OTCLK1 CK SR OCE OTCLK2 IQ1 D CE ICLK1 CK SR ICE IQ2 D CE ICLK2 CK SR ...

Page 14

Spartan-3 FPGA Family: Functional Description According to Figure 5, the clock line OTCLK1 connects the CK inputs of the upper registers on the output and three-state paths. Similarly, OTCLK2 connects the CK inputs for the lower registers on the output ...

Page 15

R DCM 180˚ 0˚ CLK1 DDR MUX D2 Q2 CLK2 Figure 6: Clocking the DDR Register Pull-Up and Pull-Down Resistors The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. ...

Page 16

Spartan-3 FPGA Family: Functional Description Together with placing the appropriate I/O symbol, two exter- nally applied voltage levels, V CCO desired signal standard. The V CCO the output driver. The voltage on these lines determines the output voltage swing for ...

Page 17

R match the characteristic impedance of the transmission line. This adjustment process compensates for differences in I/O impedance that can result from normal variation in the ambient temperature, the supply voltage and the manufac- turing process. When the output driver ...

Page 18

Spartan-3 FPGA Family: Functional Description Table 9: DCI I/O Standards (Continued) Category of Signal Signal Standard Standard (IOSTANDARD) Differential Low-Voltage LVDS_25_DCI Differential LVDSEXT_25_DCI Signalling Notes: 1. DCI signal standards are not supported in Bank 5 of any Spartan-3 FPGA packaged ...

Page 19

R Table 10: DCI Terminations Termination Controlled impedance output driver Controlled output driver with half impedance Single resistor Split resistors Split resistors with output driver impedance fixed to 25Ω Notes: 1. The value equivalent to the characteristic ...

Page 20

Spartan-3 FPGA Family: Functional Description The DCI feature operates independently for each of the device’s eight banks. Each bank has an ‘N’ reference pin (VRN) and a ‘P’ reference pin, (VRP), to calibrate driver and termination resistance. Only when using ...

Page 21

R Xilinx development software checks for this. Tables 7, 8, and 9 describe how different standards use the V supply. 4. Only one of the following standards is allowed on outputs per bank: LVDS, LDT, LVDS_EXT, or RSDS ...

Page 22

Spartan-3 FPGA Family: Functional Description . Switch Matrix SHIFTOUT SHIFTIN CLB Overview For more details on the CLBs, refer to the “Using Config- urable Logic Blocks” chapter in UG331. The Configurable Logic Blocks (CLBs) constitute the main logic resource for ...

Page 23

R Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can depending on the slice. In this position, the ...

Page 24

Spartan-3 FPGA Family: Functional Description The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. The carry chain enters the slice as CIN and exits as COUT. Five multiplexers control the chain: ...

Page 25

... Arrangement of RAM Blocks on Die The XC3S50 has one column of block RAM. The Spartan-3 devices ranging from the XC3S200 to XC3S2000 have two columns of block RAM. The XC3S4000 and XC3S5000 have four columns. The position of the columns on the die is shown in Figure 1, page 4 ...

Page 26

Spartan-3 FPGA Family: Functional Description RAMB16_Sw WEA ENA SSRA CLKA ADDRA[r –1:0] A DIA[w –1:0] A DIPA[3:0] WEB ENB SSRB CLKB ADDRB[r –1:0] B DIB[w –1:0] B DIPB[3:0] (a) Dual-Port Notes and w are integers representing the total ...

Page 27

R Table 12: Block RAM Port Signals (Continued) Port A Port B Signal Signal Signal Description Name Data Output DOA Bus Parity Data DOPA Output(s) Write Enable WEA Clock Enable ENA Set/Reset SSRA Clock CLKA Port Aspect Ratios On a ...

Page 28

Spartan-3 FPGA Family: Functional Description Block RAM automatically performs a bus-matching func- tion. When data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effec- tively combine ...

Page 29

R CLK WE DI ADDR DO 0000 EN DISABLED Figure 13: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is ...

Page 30

Spartan-3 FPGA Family: Functional Description CLK WE DI ADDR DO 0000 EN DISABLED Figure 15: Waveforms of Block RAM Data Operations with NO_CHANGE Selected Dedicated Multipliers All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to ...

Page 31

R Table 14: Embedded Multiplier Primitives Descriptions Signal Name Direction A[17:0] Input Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK. B[17:0] Input Apply the other 18-bit multiplicand ...

Page 32

Spartan-3 FPGA Family: Functional Description PSINCDEC PSEN PSCLK CLKIN CLKFB RST Figure 17: DCM Functional Blocks and Associated Signals The DCM has four functional Delay-Locked Loop (DLL), the Digital Frequency Synthe- sizer (DFS), the Phase Shifter (PS), and the Status ...

Page 33

R The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 15. The clock outputs drive simulta- neously; however, the High Frequency ...

Page 34

Spartan-3 FPGA Family: Functional Description Table 16: DLL Attributes Attribute CLK_FEEDBACK DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2 CLKDV_DIVIDE DUTY_CYCLE_CORRECTION DLL Clock Input Connections An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the glo- bal clock ...

Page 35

R FPGA CLK90 BUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 CLK0 (a) On-Chip with CLK0 Feedback FPGA CLK90 IBUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 IBUFG CLK0 (c) Off-Chip with CLK0 Feedback Notes: 1. ...

Page 36

Spartan-3 FPGA Family: Functional Description Their relative timing in the Low Frequency Mode is shown in Figure 20. The CLK90, CLK180 and CLK270 outputs are not available when operating in the High Frequency mode. (See the description of the DLL_FREQUENCY_MODE ...

Page 37

R Digital Frequency Synthesizer (DFS) The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input and a ratio of two user-determined integers. Because of the wide range of possible ...

Page 38

Spartan-3 FPGA Family: Functional Description DFS Clock Output Connections There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illus- trated in Figure 19a and Figure 19c, respectively. This is similar ...

Page 39

R Table 19: PS Attributes Attribute CLKOUT_PHASE_SHIFT Disables PS component or chooses between Fixed Phase and Variable Phase modes. PHASE_SHIFT Determines size and direction of initial fine phase shift. Notes: 1. The practical range of values will be less when ...

Page 40

Spartan-3 FPGA Family: Functional Description Table 20: Signals for Variable Phase Mode Signal Direction (1) PSEN Input Enables PSCLK for variable phase adjustment. (1) PSCLK Input Clock to synchronize phase shift adjustment. (1) PSINCDEC Input Chooses between increment and decrement ...

Page 41

R Table 22: DCM STATUS Bus Bit Name 0 Phase Shift A value of 1 indicates a phase shift overflow when one of two conditions occurs: Overflow • • 1 CLKIN Input A value of 1 indicates that the CLKIN ...

Page 42

Spartan-3 FPGA Family: Functional Description Table 24: BUFGMUX Select Mechanism S Input 0 1 The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup ...

Page 43

R 4 DCM 4 DCM DS099-2 (v2.2) May 25, 2007 Product Specification GCLK6 GCLK4 GCLK5 GCLK7 4 4 BUFGMUX 4 • • • Horizontal Spine • • • BUFGMUX 4 GCLK3 GCLK1 GCLK2 GCLK0 Figure 22: ...

Page 44

Spartan-3 FPGA Family: Functional Description Interconnect Interconnect (or routing) passes signals among the various functional elements of Spartan-3 devices. There are four kinds of interconnect: Long lines, Hex lines, Double lines, and Direct lines. Long lines connect to one out ...

Page 45

... XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 The Dual-Purpose configuration pins comprise INIT_B, DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of these pins, according to its bank placement, uses the V lines for either Bank 4 (VCCO_4 on most packages, VCCO_BOTTOM on TQ144 and CP132 packages) or Bank www ...

Page 46

Spartan-3 FPGA Family: Functional Description 5 (VCCO_5). All the signals used in the serial configuration modes rely on VCCO_4 power. Signals used in the parallel configuration modes and Readback require from VCCO_5 as well as from VCCO_4. Both the Dedicated ...

Page 47

R 3.3V: XCF0xS 1.8V: XCFxxP V CCO V CCINT Platform Flash PROM XCF0xS or XCFxxP OE/RESET GND Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for ...

Page 48

Spartan-3 FPGA Family: Functional Description when operating in the User mode. This is accomplished by setting the Persist option to Yes. Multiple FPGAs can be configured using the Slave Parallel mode and can be made to start-up simultaneously. Figure 25 ...

Page 49

R Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA to be configured in the chain shown above (or for the single FPGA ...

Page 50

Spartan-3 FPGA Family: Functional Description Figure 27: Configuration Flow Diagram for the Serial and Parallel Modes 50 54 Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 4 > 1V CCO ...

Page 51

R and V No (JTAG port becomes No Figure 28: Boundary-Scan Configuration Flow Diagram DS099-2 (v2.2) May 25, 2007 Product Specification Set PROG_B Low Power-On after Power-On V >1V CCINT and V > CCAUX Bank 4 > 1V ...

Page 52

... Xilinx FPGAs, including some with integrated multi-rail regulators specifically designed for Spartan-3 FPGAs. The vendor solution guides as well as Xilinx power estimation and analysis tools. Power Distribution System (PDS) Design and Bypass/Decoupling Capacitors Good power distribution system (PDS) design is important ...

Page 53

R threshold levels (see Table 28, page supplies reach their respective threshold, the POR reset is released and the FPGA begins its configuration process. Because the three supply inputs must be valid to release the POR reset and can be ...

Page 54

Spartan-3 FPGA Family: Functional Description Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release 05/19/03 1.1 Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions. 07/11/03 1.2 Explained the configuration port Persist option in Updated for the XC3S50 ...

Page 55

R DS099-3 (v2.2) May 25, 2007 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...

Page 56

Spartan-3 FPGA Family: DC and Switching Characteristics Table 27: Absolute Maximum Ratings (Continued) Symbol Description V Electrostatic Discharge Voltage pins relative ESD to GND T Junction temperature J T Soldering temperature SOL T Storage temperature STG Notes: 1. Stresses beyond ...

Page 57

... Spartan-3 FPGA Family: DC and Switching Characteristics (2) Top Marking Device Mask revisions ‘A’ XC3S50 through ‘D’ XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Mask revisions ‘E’ or All later Devices with ‘FQ’ All fabrication/process code not specifically ordered with SCD0961 Devices with ‘GQ’ ...

Page 58

Spartan-3 FPGA Family: DC and Switching Characteristics Table 31: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX ΔV (2) Voltage variance on ...

Page 59

R Table 32: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued) Symbol Description (3) R Equivalent resistance of pull-down resistor PD at User I/O, Dual-Purpose, and Dedicated pins, driven from I RPD R Value of external reference ...

Page 60

... XC3S4000 XC3S5000 XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 supply current XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 31. Quiescent supply current is measured with all I/O drivers of 25° 1.26V 3.45V, and V = 2.625V. The FPGA is programmed with a "blank" CCO ...

Page 61

R Table 34: Recommended Operating Conditions for User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) Min (V) Nom (V) (3) GTL - GTL_DCI - (3) GTLP - GTLP_DCI - HSLVDCI_15 1.4 HSLVDCI_18 1.7 HSLVDCI_25 2.3 HSLVDCI_33 3.0 HSTL_I, HSTL_I_DCI 1.4 ...

Page 62

Spartan-3 FPGA Family: DC and Switching Characteristics Table 35: DC Characteristics of User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) GTL GTL_DCI GTLP GTLP_DCI HSLVDCI_15 HSLVDCI_18 HSLVDCI_25 HSLVDCI_33 HSTL_I HSTL_I_DCI HSTL_III HSTL_III_DCI HSTL_I_18 HSTL_I_DCI_18 HSTL_II_18 ...

Page 63

R Table 35: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) (4) LVCMOS33 LVDCI_33, LVDCI_DV2_33 (4) LVTTL ...

Page 64

Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic V V GND level Table 36: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO Signal Standard Min Nom (IOSTANDARD) (V) (V) LDT_25 (ULVDS_25) 2.375 2.50 LVDS_25, 2.375 ...

Page 65

R Internal Logic V OUTN V OUTP GND level Table 37: DC Characteristics of User I/Os Using Differential Signal Standards (1) Mask Signal Standard Revision LDT_25 (ULVDS_25) All LVDS_25 All ‘E’ (6) BLVDS_25 All LVDSEXT_25 All ‘E’ (6) LVPECL_25 All ...

Page 66

... Xilinx development software) and back-annotated to the simulation netlist. Table 38: Spartan-3 Speed Grade Designations (ISE v8.2i or later) Device Advance XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 www.xilinx.com R more precise, and Preliminary Production –4, –5 (v1.37 and later) – ...

Page 67

... XC3S4000 XC3S5000 (2) LVCMOS25 , XC3S50 12mA output drive, XC3S200 Fast slew rate, XC3S400 without DCM XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 Table 43. If the latter is true, add the appropriate Output adjustment from www.xilinx.com Speed Grade -MIN -5 -4 Min Max Max 0.78 2.04 2 ...

Page 68

... XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (3) LVCMOS25 , XC3S50 IOBDELAY = NONE, XC3S200 (4) with DCM XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (3) LVCMOS25 , XC3S50 IOBDELAY = IFD, XC3S200 without DCM XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set www.xilinx.com ...

Page 69

... XC3S50 -0.55 -0.55 XC3S200 -0.29 -0.29 XC3S400 -0.29 -0.29 XC3S1000 -0.55 -0.55 XC3S1500 -0.55 -0.55 XC3S2000 -0.55 -0.55 XC3S4000 -0.61 -0.61 XC3S5000 -0.68 -0.68 XC3S50 -2.74 -2.74 XC3S200 -3.00 -3.00 XC3S400 -2.90 -2.90 XC3S1000 -3.24 -3.24 XC3S1500 -3.55 -3.55 XC3S2000 -4 ...

Page 70

... XC3S50 IOBDELAY = NONE XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (2) LVCMOS25 , XC3S50 IOBDELAY = IFD XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set Table 43. www.xilinx.com R Speed Grade -5 -4 Max Max Units 2.01 2.31 ns 1.50 1. ...

Page 71

R Table 43: Input Timing Adjustments for IOB Add the Adjustment Below Convert Input Time from LVCMOS25 to the Speed Grade Following Signal Standard (IOSTANDARD) -5 Single-Ended Standards GTL, GTL_DCI 0.44 GTLP, GTLP_DCI 0.36 HSLVDCI_15 0.51 HSLVDCI_18 0.29 HSLVDCI_25 0.51 ...

Page 72

... XC3S200 output drive, Fast slew XC3S400 rate XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 XC3S200 XC3S400 XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (2) LVCMOS25 , 12mA XC3S200 output drive, Fast slew XC3S400 rate XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 All Table 47 and are based on the operating conditions set Table 46 ...

Page 73

... XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 LVCMOS25, 12mA All output drive, Fast slew rate XC3S200 XC3S400 XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set Table 46. www.xilinx.com Speed Grade - Min Max Max Units 0.28 0.74 ...

Page 74

Spartan-3 FPGA Family: DC and Switching Characteristics Table 46: Output Timing Adjustments for IOB Convert Output Time from Adjustment Below LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) -MIN Single-Ended Standards GTL 0 GTL_DCI ...

Page 75

R Table 46: Output Timing Adjustments for IOB (Continued) Convert Output Time from Adjustment Below LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) -MIN LVCMOS33 Slow ...

Page 76

Spartan-3 FPGA Family: DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test condi- tions. Table 47 presents the conditions to use for each stan- dard. The method ...

Page 77

R Table 47: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V (V) REF LVCMOS18 - LVDCI_18 LVDCI_DV2_18 LVCMOS25 - LVDCI_25 LVDCI_DV2_25 LVCMOS33 - LVDCI_33 LVDCI_DV2_33 LVTTL - PCI33_3 Rising - Falling SSTL18_I 0.9 SSTL18_I_DCI SSTL18_II 0.9 ...

Page 78

Spartan-3 FPGA Family: DC and Switching Characteristics The capacitive load ( connected between the output L and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on ...

Page 79

... XC3S400 - - XC3S1000 - - XC3S1500 - - XC3S2000 - - XC3S4000 - - XC3S5000 - - Notes: 1. The V lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each CCO pair of interconnected banks shares three V 2. The information in this table also applies to Pb-free packages. DS099-3 (v2.2) May 25, 2007 ...

Page 80

Spartan-3 FPGA Family: DC and Switching Characteristics Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 Single-Ended Standards GTL 0 0 GTL_DCI 0 0 GTLP 0 0 GTLP_DCI 0 ...

Page 81

R Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Continued) CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 LVCMOS33 Slow ...

Page 82

Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic Timing Table 50: CLB Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, CKO the time from the active transition at the CLK input to data appearing at ...

Page 83

R Table 51: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data SHCKO appearing on the distributed RAM output Setup Times T Setup time of data at the BX ...

Page 84

Spartan-3 FPGA Family: DC and Switching Characteristics Table 53: Synchronous Multiplier Timing Symbol Description Clock-to-Output Times T When reading from the MULTCK Multiplier, the time from the active transition at the C clock input to data appearing ...

Page 85

R Table 55: Block RAM Timing Symbol Description Clock-to-Output Times T When reading from the Block BCKO RAM, the time from the active transition at the CLK input to data appearing at the DOUT output Setup Times T Time from ...

Page 86

Spartan-3 FPGA Family: DC and Switching Characteristics Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Fre- quency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL ...

Page 87

... XC3S400 - 250 - 250 ± ± XC3S1000 - 400 - 400 ± ± XC3S1500 - 400 - 400 ± ± XC3S2000 - 400 - 400 ± ± XC3S4000 - 400 - 400 ± ± XC3S5000 - 400 - 400 ± ± All - 150 - 150 ± ± - 140 - 140 ± ± - 250 ...

Page 88

Spartan-3 FPGA Family: DC and Switching Characteristics Table 58: Switching Characteristics for the DLL (Continued) Symbol Lock Time LOCK_DLL When using the DLL alone: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED ...

Page 89

... XC3S400 - 250 - ± ± XC3S1000 - 400 - ± ± XC3S1500 - 400 - ± ± XC3S2000 - 400 - ± ± XC3S4000 - 400 - ± ± XC3S5000 - 400 - ± ± All - 300 - All - 10.0 - 10.0 All - 10.0 - 10.0 Table 59. provides an estimate. Use the DCM Clock Wizard 7 ...

Page 90

Spartan-3 FPGA Family: DC and Switching Characteristics Phase Shifter (PS) Phase Shifter operation is only supported if the DLL is in the Low frequency mode, see Table 61: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Description ...

Page 91

R Miscellaneous DCM Timing Table 63: Miscellaneous DCM Timing Symbol DCM_INPUT_CLOCK_STOP Maximum duration that the CLKIN and CLKFB signals can be stopped DCM_RST_PW_MIN Minimum duration of a RST pulse width (3) DCM_RST_PW_MAX Maximum duration of a RST pulse width (4) ...

Page 92

... XC3S200 - 5 XC3S400 - 5 XC3S1000 - 5 XC3S1500 - 7 XC3S2000 - 7 XC3S4000 - 7 XC3S5000 - 7 All 0.3 - XC3S50 - 2 XC3S200 - 2 XC3S400 - 2 XC3S1000 - 2 XC3S1500 - 3 XC3S2000 - 3 XC3S4000 - 3 XC3S5000 - 3 All 250 - All 0.5 4.0 Table 31. This means power must be applied to all DS099-3 (v2.2) May 25, 2007 Product Specification R 1.2V 2.5V Units μ μs ...

Page 93

R PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 35: Waveforms for Master and Slave Serial Configuration Table 65: Timing for the Master and Slave Serial Configuration Modes Symbol Clock-to-Output Times T The time from the falling ...

Page 94

Spartan-3 FPGA Family: DC and Switching Characteristics PROG_B (Input) INIT_B (Open-Drain) CS_B (Input) RDWR_B (Input) CCLK (Input/Output (Inputs) High-Z BUSY (Output) Notes: 1. Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration. Figure 36: ...

Page 95

R Table 66: Timing for the Master and Slave Parallel Configuration Modes (Continued) Symbol Hold Times T The time from the rising transition at the CCLK pin to the point SMCCD when data is last held at the D0-D7 pins ...

Page 96

Spartan-3 FPGA Family: DC and Switching Characteristics TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 67: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the TCK pin to data ...

Page 97

... Production status. Removed V (Table 29). Added equivalent resistance values for internal pull-up and pull-down resistors worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000 temperature range specification and improved typical quiescent current values minimum clock input frequency specification from 24 MHz down to 18 MHz ...

Page 98

Spartan-3 FPGA Family: DC and Switching Characteristics Date Version No. 04/03/06 2.0 Upgraded Module 3, removing Preliminary status. Moved XC3S5000 to Production status in Finalized I/O timing on XC3S5000 for v1.38 speed files. Added minimum timing values for various logic ...

Page 99

R DS099-4 (v2.2) May 25, 2007 Introduction This data sheet module describes the various pins on a Spartan™-3 FPGA and how they connect to the supported component packages. • The Pin Types section categorizes all of the FPGA pins by ...

Page 100

Spartan-3 FPGA Family: Pinout Descriptions Table 68: Types of Pins on Spartan-3 FPGAs (Continued) Type/ Color Code VREF Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in the same bank, provides a reference ...

Page 101

R Table 69: Spartan-3 Pin Definitions Pin Name Direction I/O: General-purpose I/O pins I/O User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output I/O_Lxxy_# User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output DUAL: Dual-purpose configuration ...

Page 102

Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 Pin Definitions (Continued) Pin Name Direction IO_Lxxy_#/INIT_B Bidirectional (open-drain) during configuration User I/O after configuration DCI: Digitally Controlled Impedance reference resistor input pins IO_Lxxy_#/VRN_# or Input when using DCI IO/VRN_# Otherwise, same ...

Page 103

R Table 69: Spartan-3 Pin Definitions (Continued) Pin Name Direction DONE Bidirectional with open-drain or totem-pole Output M0, M1, M2 Input HSWAP_EN Input JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN pin) TCK ...

Page 104

Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 Pin Definitions (Continued) Pin Name Direction VCCAUX: Auxiliary voltage supply pins VCCAUX Supply VCCINT: Internal core voltage supply pins VCCINT Supply GND: Ground supply pins GND Supply N.C.: Unconnected package pins N.C. ...

Page 105

R Bank 0 Bank 1 Bank 5 Bank 4 DUAL Type: Dual-Purpose Configuration and I/O Pins These pins serve dual purposes. The user-I/O pins are tem- porarily borrowed during the configuration process to load configuration data into the FPGA. After ...

Page 106

Spartan-3 FPGA Family: Pinout Descriptions Table 70: Dual-Purpose Pins Used in Master or Slave Serial Mode Pin Name Direction DIN Input Serial Data Input: During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and ...

Page 107

R Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B ...

Page 108

Spartan-3 FPGA Family: Pinout Descriptions Table 71: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Continued) Pin Name Direction RDWR_B Input Read/Write Control for Parallel Mode Configuration: In Master and Slave Parallel modes, assert this pin Low together with CS_B ...

Page 109

R One of eight I/O Banks User I/O User I/O (a) No termination DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires ...

Page 110

Spartan-3 FPGA Family: Pinout Descriptions CCLK: Configuration Clock The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an input-only pin for the Slave Serial and Slave Parallel config- uration modes. ...

Page 111

R Table 73: DonePin and DriveDone Bitstream Option Interaction Single- or Multi- DonePin DriveDone FPGA Design Pullnone No Single Pullnone No Pullnone Yes Single Pullnone Yes Pullup No Single Pullup No Pullup Yes Single Pullup Yes M2, M1, M0: Configuration ...

Page 112

... XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 49. XC3S2000 XC3S4000 XC3S5000 TDO Using JTAG Port After Configuration The JTAG port is always active and available before, during, and after FPGA configuration. Add the BSCAN_SPARTAN3 primitive to the design to create user-defined JTAG instruc- tions and JTAG chains to communicate with internal logic. ...

Page 113

R The TDO output can directly drive a 3.3V input but with reduced noise immunity. See 3.3V-Tolerant Configuration Interface, page 46 or XAPP453: The 3.3V Configuration of for additional details. Spartan-3 FPGAs The following interface precautions are recommended when connecting ...

Page 114

Spartan-3 FPGA Family: Pinout Descriptions VCCAUX Type: Voltage Supply for Auxiliary Logic The VCCAUX pins supply power to various auxiliary cir- cuits, such as to the Digital Clock Managers (DCMs), the JTAG pins, and to the dedicated configuration pins (CON- ...

Page 115

R Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> IO_Lxxy_#/ D5 IO_Lxxy_#/ D6 IO_Lxxy_#/ D7 IO_Lxxy_#/ CS_B IO_Lxxy_#/ RDWR_B IO_Lxxy_#/ DOUT (O) BUSY/DOUT DUAL: Dual-purpose configuration pins (INIT_B has a pull-up resistor to ...

Page 116

Spartan-3 FPGA Family: Pinout Descriptions Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> M1 M1=0 (I) M0 M0=0 (I) HSWAP_EN HSWAP_EN (I) JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during ...

Page 117

R Bitstream Options Table 79 lists the various bitstream options that affect pins on a Spartan-3 FPGA. The table shows the names of the affected pins, describes the function of the bitstream option, Table 79: Bitstream Options Affecting Spartan-3 Pins ...

Page 118

Spartan-3 FPGA Family: Pinout Descriptions Table 79: Bitstream Options Affecting Spartan-3 Pins (Continued) Affected Pin Name(s) M0 After configuration, this bitstream option either pulls M0 to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows M0 ...

Page 119

R Selecting the Right Package Option Spartan-3 FPGAs are available in both quad-flat pack (QFP) and ball grid array (BGA) packaging options. While QFP packaging offers the lowest absolute cost, the BGA Table 81: Comparing Spartan-3 Packaging Options Characteristic Maximum ...

Page 120

Spartan-3 FPGA Family: Pinout Descriptions Power, Ground, and I/O by Package Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return, GND. The numbers of pins dedicated to these functions varies by package, as shown ...

Page 121

... FG456 XC3S1000 FG456 XC3S1500 FG456 XC3S2000 FG456 XC3S1000 FG676 XC3S1500 FG676 XC3S2000 FG676 XC3S4000 FG676 XC3S2000 FG900 XC3S4000 FG900 XC3S5000 FG900 XC3S4000 FG1156 XC3S5000 FG1156 Electronic versions of the package pinout tables and foot- prints are available for download from the Xilinx website. ...

Page 122

... FG456 XC3S400 8.1 XC3S1000 6.7 XC3S1500 4.8 XC3S2000 3.7 FG676 XC3S1000 6.3 XC3S1500 4.9 XC3S2000 4.1 XC3S4000 3.7 FG900 XC3S2000 3.7 XC3S4000 3.2 XC3S5000 2.9 FG1156 XC3S4000 1.9 XC3S5000 1.9 122 age body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ ...

Page 123

R VQ100: 100-lead Very-thin Quad Flat Package The XC3S50 and the XC3S200 devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices share a common footprint for this package as shown in Table 86 and Figure 42. ...

Page 124

Spartan-3 FPGA Family: Pinout Descriptions Table 86: VQ100 Package Pinout XC3S50 XC3S200 Bank Pin Name 7 IO_L40N_7/VREF_7 7 IO_L40P_7 7 VCCO_7 N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A ...

Page 125

R VQ100 Footprint IO_L01P_7/VRN_7 1 2 IO_L01N_7/VRP_7 GND 3 IO_L21P_7 4 IO_L21N_7 5 6 VCCO_7 7 VCCAUX IO_L23P_7 8 IO_L23N_7 9 10 GND IO_L40P_7 11 IO_L40N_7/VREF_7 12 IO_L40P_6/VREF_6 13 IO_L40N_6 14 IO_L24P_6 15 IO_L24N_6/VREF_6 VCCINT 19 ...

Page 126

Spartan-3 FPGA Family: Pinout Descriptions CP132: 132-ball Chip-Scale Package The XC3S50 is available in the 132-ball chip-scale pack- age, CP132. The pinout and footprint for this package appear in Table 88 and Figure 44. All the package pins appear in ...

Page 127

R Table 88: CP132 Package Pinout Bank XC3S50 Pin Name 6 IO_L20N_6 6 IO_L20P_6 6 IO_L22N_6 6 IO_L22P_6 6 IO_L23N_6 6 IO_L23P_6 6 IO_L24N_6/VREF_6 6 IO_L24P_6 6 IO_L40N_6 6 IO_L40P_6/VREF_6 7 IO_L01N_7/VRP_7 7 IO_L01P_7/VRN_7 7 IO_L21N_7 7 IO_L21P_7 7 IO_L22N_7 ...

Page 128

Spartan-3 FPGA Family: Pinout Descriptions User I/Os by Bank Table 89 indicates how the 89 available user-I/O pins are distributed between the eight I/O banks on the CP132 pack- Table 89: User I/Os Per Bank for XC3S50 in CP132 Package ...

Page 129

R CP132 Footprint I/O VCCO_ A PROG_B TDI L01N_0 VRP_0 I/O I/O HSWAP_ B L01P_7 L01N_7 EN VRN_7 VRP_7 VCCO_ I/O C GND L01P_0 LEFT L21N_7 VRN_0 I/O I/O I/O D L22N_7 L22P_7 L21P_7 I/O I/O I/O ...

Page 130

... Spartan-3 FPGA Family: Pinout Descriptions TQ144: 144-lead Thin Quad Flat Package The XC3S50, the XC3S200, and the XC3S400 are avail- able in the 144-lead thin quad flat package, TQ144. Conse- quently, there is only one footprint for this package as shown in Table 90 and Figure 44 ...

Page 131

... VCCAUX P115 VCCO VCCAUX P106 VCCO VCCAUX P75 VCCO VCCAUX P91 VCCO P54 VCCO www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions XC3S50 XC3S200 XC3S400 TQ144 Pin Pin Name Number VCCO_BOTTOM P43 VCCO_BOTTOM P66 VCCO_LEFT P19 VCCO_LEFT P34 VCCO_LEFT P3 GND P136 GND P139 ...

Page 132

Spartan-3 FPGA Family: Pinout Descriptions User I/Os by Bank Table 91 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the TQ144 pack- age. Table 91: User I/Os Per Bank in TQ144 Package Package ...

Page 133

R TQ144 Footprint IO_L01P_7/VRN_7 1 IO_L01N_7/VRP_7 2 X VCCO_LEFT 3 IO/VREF_7 4 IO_L20P_7 5 IO_L20N_7 6 IO_L21P_7 7 IO_L21N_7 8 GND 9 IO_L22P_7 10 IO_L22N_7 11 IO_L23P_7 12 IO_L23N_7 13 IO_L24P_7 14 IO_L24N_7 15 GND 16 IO_L40P_7 17 IO_L40N_7/VREF_7 18 ...

Page 134

... XC3S50 maps to a VREF-type pin on the XC3S200 and XC3S400. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C. pin on the XC3S50 to the same VREF voltage ...

Page 135

... P127 VCCO 5 IO_L28P_5/ P93 I/O D7 P97 I/O 5 IO_L31N_5/ P85 VREF D4 P96 VREF 5 IO_L31P_5/ D5 www.xilinx.com XC3S200 PQ208 XC3S50 XC3S400 Pin Pin Name Pin Name Number IO/VREF_4 P102 IO_L01N_4/ P101 VRP_4 IO_L01P_4/ P100 VRN_4 IO_L25N_4 P95 IO_L25P_4 P94 IO_L27N_4/ P92 DIN/D0 IO_L27P_4/ P90 D1 ...

Page 136

... N/A GND P7 I/O N/A GND P11 I/O N/A GND P10 I/O N/A GND P13 I/O www.xilinx.com XC3S200 PQ208 XC3S50 XC3S400 Pin Pin Name Pin Name Number IO_L21P_7 P12 IO_L22N_7 P16 IO_L22P_7 P15 IO_L23N_7 P19 IO_L23P_7 P18 IO_L24N_7 P21 IO_L24P_7 P20 IO_L39N_7 ...

Page 137

... I/O banks for the XC3S50 in the P70 VCCINT PQ208 package. Similarly, P104 CONFIG able user-I/O pins are distributed between the eight I/O P103 CONFIG banks for the XC3S200 and XC3S400 in the PQ208 pack- age. All Possible I/O Pins by Type Maximum I/O I/O DUAL 15 9 ...

Page 138

... Spartan-3 FPGA Family: Pinout Descriptions Table 94: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package Package Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 138 All Possible I/O Pins by Type Maximum I/O I/O DUAL www.xilinx.com DCI VREF GCLK ...

Page 139

R DS099-4 (v2.2) May 25, 2007 Product Specification Spartan-3 FPGA Family: Pinout Descriptions www.xilinx.com 139 ...

Page 140

... I/O) I/O: Unrestricted, 72 general-purpose user I/O VREF: User I/O or input 16 voltage reference for bank N.C.: Unconnected pins for 17 XC3S50 ( ) XC3S200, XC3S400 (141 max user I/O) I/O: Unrestricted, 83 general-purpose user I/O VREF: User I/O or input 22 voltage reference for bank N.C.: No unconnected pins 0 ...

Page 141

R Bank 1 Bank 4 DS099-4 (v2.2) May 25, 2007 Product Specification Spartan-3 FPGA Family: Pinout Descriptions IO_L01N_2/VRP_2 156 IO_L01P_2/VRN_2 155 IO/VREF_2 ( ) 154 VCCO_2 153 IO_L19N_2 152 GND 151 IO_L19P_2 150 IO_L20N_2 149 IO_L20P_2 148 IO_L21N_2 147 IO_L21P_2 ...

Page 142

... FT256: 256-lead Fine-pitch Thin Ball Grid Array The 256-lead fine-pitch thin ball grid array package, FT256, supports three different Spartan-3 devices, including the XC3S200, the XC3S400, and the XC3S1000. The footprints for all three devices are identical, as shown in Figure 46. All the package pins appear in Table 95 bank number, then by pin name ...

Page 143

... T14 I/O 5 N12 VREF 5 P13 VREF 5 T10 VREF 5 R13 DCI 5 T13 DCI www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions XC3S200 XC3S400 FT256 XC3S1000 Pin Pin Name Number IO_L25N_4 P12 IO_L25P_4 R12 IO_L27N_4/DIN/D0 M11 IO_L27P_4/D1 N11 IO_L28N_4 P11 IO_L28P_4 R11 IO_L29N_4 M10 IO_L29P_4 ...

Page 144

... N/A C3 VREF N/A D1 I/O N/A D2 I/O N/A E3 VREF N/A D3 I/O N/A E1 I/O N/A E2 I/O N/A F4 I/O N/A E4 I/O N/A www.xilinx.com XC3S200 XC3S400 FT256 XC3S1000 Pin Pin Name Number IO_L22N_7 F2 IO_L22P_7 F3 IO_L23N_7 G5 IO_L23P_7 F5 IO_L24N_7 G3 IO_L24P_7 G4 IO_L39N_7 H3 IO_L39P_7 H4 IO_L40N_7/VREF_7 H1 IO_L40P_7 G1 VCCO_7 G6 VCCO_7 H5 VCCO_7 ...

Page 145

... All Possible I/O Pins by Type Maximum I/O I/O DUAL www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions XC3S200 XC3S400 FT256 XC3S1000 Pin Pin Name Number VCCINT N4 VCCINT N13 T15 R14 C14 A2 A15 C13 indicates how the available user-I/O pins are dis- DCI VREF ...

Page 146

Spartan-3 FPGA Family: Pinout Descriptions FT256 Footprint I TDI GND L01P_0 VREF_0 VRN_0 I/O I/O B PROG_B L01P_7 GND L01N_0 VRN_7 VRP_0 I/O I/O I/O HSWAP_ C L01N_7 L16P_7 L16N_7 EN VRP_7 VREF_7 I/O ...

Page 147

... R FG320: 320-lead Fine-pitch Ball Grid Array The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3 devices, including the XC3S400, the XC3S1000, and the XC3S1500. The foot- print for all three devices is identical, as shown in and Figure 47. The FG320 package array of solder balls minus the four center balls ...

Page 148

... I/O 4 N15 I/O 4 M14 I/O 4 N14 I/O 4 M15 I/O 4 M16 VREF 4 M18 I/O 4 N17 I/O www.xilinx.com XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number IO_L27N_3 L14 IO_L27P_3 L13 IO_L34N_3 L15 IO_L34P_3/VREF_3 L16 IO_L35N_3 L18 IO_L35P_3 L17 IO_L39N_3 K13 IO_L39P_3 K14 IO_L40N_3/VREF_3 ...

Page 149

... VCCO DCI 7 T2 DCI VREF I/O 7 www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number IO_L21N_6 N4 IO_L21P_6 P4 IO_L22N_6 N5 IO_L22P_6 M5 IO_L23N_6 M3 IO_L23P_6 M4 IO_L24N_6/VREF_6 N2 IO_L24P_6 M1 IO_L27N_6 L6 IO_L27P_6 L5 IO_L34N_6/VREF_6 L3 IO_L34P_6 L4 IO_L35N_6 L2 IO_L35P_6 L1 IO_L39N_6 K5 IO_L39P_6 ...

Page 150

... GND VCCAUX TCK L11 GND VCCAUX TDI L8 GND VCCAUX TDO L9 GND VCCAUX TMS M12 GND M7 GND N1 GND N18 GND T10 GND www.xilinx.com XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number GND T9 GND U17 GND U2 GND V1 GND V13 GND V18 GND V6 VCCAUX ...

Page 151

R User I/Os by Bank Table 98 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the FG320 pack- age. Table 98: User I/Os Per Bank in FG320 Package Maximum Package Edge I/O Bank ...

Page 152

Spartan-3 FPGA Family: Pinout Descriptions FG320 Footprint Bank I/O I/O I/O I/O A GND L01N_0 L01P_0 L15N_0 L15P_0 VRP_0 VRN_0 I/O I/O I/O I/O B GND L16P_7 VREF_0 L09N_0 L25N_0 VREF_7 I/O I/O I/O ...

Page 153

... XC3S2000. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C. pin on the XC3S400 to the same VREF voltage. This provides maximum flexibility as you could potentially migrate a design from the XC3S400 device to an XC3S1000, an XC3S1500 XC3S2000 FPGA without changing the printed circuit board ...

Page 154

Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 1 IO/VREF_1 IO/VREF_1 1 N. IO/VREF_1 1 IO_L01N_1/ IO_L01N_1/ VRP_1 VRP_1 1 IO_L01P_1/ IO_L01P_1/ VRN_1 VRN_1 1 IO_L06N_1/ ...

Page 155

R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 2 IO_L40P_2/ IO_L40P_2/ VREF_2 VREF_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 ...

Page 156

Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 4 IO_L24P_4 IO_L24P_4 4 IO_L25N_4 IO_L25N_4 4 IO_L25P_4 IO_L25P_4 4 IO_L27N_4/ IO_L27N_4/ DIN/D0 DIN/D0 4 IO_L27P_4/ IO_L27P_4 ...

Page 157

R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 6 IO_L19N_6 IO_L19N_6 6 IO_L19P_6 IO_L19P_6 6 IO_L20N_6 IO_L20N_6 6 IO_L20P_6 IO_L20P_6 6 IO_L21N_6 IO_L21N_6 6 IO_L21P_6 IO_L21P_6 6 IO_L22N_6 IO_L22N_6 6 IO_L22P_6 IO_L22P_6 ...

Page 158

Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 7 IO_L40N_7/ IO_L40N_7/ VREF_7 VREF_7 7 IO_L40P_7 IO_L40P_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 ...

Page 159

... User I/Os by Bank Table 100 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks for the XC3S400 in the FG456 package. Similarly, Table 101 Table 100: User I/Os Per Bank for XC3S400 in FG456 Package I/O Maximum Edge Bank 0 ...

Page 160

... I/O) I/O: Unrestricted, 196 general-purpose user I/O VREF: User I/O or input 32 voltage reference for bank N.C.: Unconnected pins for 69 XC3S400 ( ) XC3S1000, XC3S1500, XC3S2000 (333 max user I/O) I/O: Unrestricted, 261 general-purpose user I/O VREF: User I/O or input 36 voltage reference for bank N ...

Page 161

R Bank I/O I/O I/O I/O L22N_1 I/O VCCAUX L30N_1 L28N_1 L25P_1 I/O I/O I/O I/O I/O I/O L22P_1 L32N_1 L30P_1 L28P_1 L25N_1 L16N_1 GCLK5 I/O I/O I/O I/O L19N_1 L32P_1 GND VCCO_1 ...

Page 162

... XC3S1000 or XC3S1500 that maps to a user-I/O pin on the XC3S2000 and XC3S4000. If the table entry is shaded tan, then the unconnected pin on either the XC3S1000 or XC3S1500 maps to a VREF-type pin on the XC3S2000 and XC3S4000 ...

Page 163

... I/O 1 VCCO_1 D21 I/O 1 VCCO_1 A21 I/O 1 VCCO_1 B21 I/O 1 VCCO_1 D20 I/O www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L09P_1 IO_L09P_1 E20 IO_L10N_1/ IO_L10N_1/ A20 VREF VREF_1 VREF_1 IO_L10P_1 IO_L10P_1 B20 IO_L11N_1 IO_L11N_1 E19 IO_L11P_1 ...

Page 164

... I/O J25 3 IO_L03P_3 I/O K21 3 N. VREF 3 N. K22 I K23 I/O www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L24P_2 IO_L24P_2 K24 IO_L26N_2 IO_L26N_2 K25 IO_L26P_2 IO_L26P_2 K26 IO_L27N_2 IO_L27N_2 L19 IO_L27P_2 IO_L27P_2 L20 IO_L28N_2 ...

Page 165

... IO_L08P_4 R24 I/O 4 IO_L09N_4 T23 I/O 4 IO_L09P_4 R26 I/O 4 IO_L10N_4 R25 VREF 4 IO_L10P_4 www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L35N_3 IO_L35N_3 P20 IO_L35P_3 IO_L35P_3 P19 IO_L38N_3 IO_L38N_3 P22 IO_L38P_3 IO_L38P_3 P21 IO_L39N_3 IO_L39N_3 P24 IO_L39P_3 ...

Page 166

... IO_L15P_5 AF14 GCLK 5 IO_L16N_5 5 IO_L16P_5 AD16 VCCO 5 N. AD20 VCCO 5 N. U14 VCCO www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number VCCO_4 VCCO_4 V14 VCCO VCCO_4 VCCO_4 V15 VCCO VCCO_4 VCCO_4 V16 VCCO VCCO_4 VCCO_4 W17 VCCO ...

Page 167

... IO_L29P_6 AD1 DCI 6 IO_L31N_6 6 IO_L31P_6 AB4 I/O 6 IO_L32N_6 AB3 I/O 6 IO_L32P_6 AC2 VREF 6 IO_L33N_6 www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L03P_6 IO_L03P_6 AC1 IO_L05N_6 IO_L05N_6 AB2 IO_L05P_6 IO_L05P_6 AB1 IO_L06N_6 IO_L06N_6 Y7 IO_L06P_6 IO_L06P_6 Y6 IO_L07N_6 IO_L07N_6 ...

Page 168

... IO_L40P_7 H7 VREF 7 VCCO_7 G1 I/O 7 VCCO_7 G2 I/O 7 VCCO_7 J6 I/O 7 VCCO_7 H5 7 VCCO_7 VREF 7 VCCO_7 www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L17N_7 IO_L17N_7 H3 IO_L17P_7 IO_L17P_7 H4 IO_L19N_7/ IO_L19N_7/ H1 VREF VREF_7 VREF_7 IO_L19P_7 IO_L19P_7 H2 IO_L20N_7 IO_L20N_7 K7 IO_L20P_7 IO_L20P_7 J7 IO_L21N_7 ...

Page 169

... N/A VCCAUX GND M23 N/A VCCAUX GND N11 N/A VCCAUX GND N12 N/A VCCAUX GND www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number GND GND N13 GND GND GND N14 GND GND GND N15 GND GND GND ...

Page 170

... XC3S1500 balls D25 and F25 are not VREF pins although they are designated as such design uses an IOSTANDARD requiring U18 VCCINT VREF in bank 2 then apply the workaround in V9 20519 VCCINT 2. XC3S4000 is pin compatible but uses alternate differential pairs on V10 VCCINT six package balls. V17 VCCINT V18 VCCINT User I/Os by Bank ...

Page 171

... Table 104: User I/Os Per Bank for XC3S1500 in FG676 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 Table 105: User I/Os Per Bank for XC3S2000 and XC3S4000 in FG676 Package Maximum Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 DS099-4 (v2.2) May 25, 2007 ...

Page 172

... I/O: Unrestricted, 403 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: Unconnected pins for 2 XC3S1500 ( ) XC3S2000, XC3S4000 (489 max user I/O) I/O: Unrestricted, 405 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: No unconnected pins ...

Page 173

... I/O I/O I/O VCCAUX I/O I/O GND L05P_4 L04P_4 DS099-4_12b_011205 www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions Right Half of Package (top view Notes Differential pair assignments shown in parentheses on J balls H20, H21, H22, H23, H24, and J21 are for XC3S4000 only 173 ...

Page 174

... Table 106. If the table entry is shaded, then there is an unconnected pin on the XC3S2000 that maps to a user-I/O pin on the XC3S4000 and XC3S5000. An electronic version of this package pinout table and foot- print diagram is available for download from the Xilinx web- site at http://www ...

Page 175

... IO_L22N_1 B27 DCI 1 IO_L22P_1 1 IO_L23N_1 D26 I/O 1 IO_L23P_1 C27 I/O 1 IO_L24N_1 A26 I/O 1 IO_L24P_1 B26 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L04N_1 B25 IO_L04P_1 C25 IO_L05N_1 F24 IO_L05P_1 F25 IO_L06N_1/ C24 VREF_1 IO_L06P_1 D24 IO_L07N_1 ...

Page 176

... IO_L24N_2 2 IO_L24P_2 C30 DCI 2 IO_L26N_2 2 IO_L26P_2 D27 I/O 2 IO_L27N_2 D28 I/O 2 IO_L27P_2 D29 VREF 2 IO_L28N_2 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L03P_2 D30 IO_L04N_2 E29 IO_L04P_2 E30 IO_L05N_2 F28 IO_L05P_2 F29 IO_L06N_2 G27 IO_L06P_2 G28 IO_L07N_2 ...

Page 177

... VCCO 3 IO_L20N_3 E28 VCCO 3 IO_L20P_3 J28 VCCO 3 IO_L21N_3 N28 VCCO 3 IO_L21P_3 AB25 I/O 3 IO_L22N_3 3 IO_L22P_3 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L01N_3/ AH30 VRP_3 IO_L01P_3/ AH29 VRN_3 IO_L02N_3/ AG28 VREF_3 IO_L02P_3 AG27 IO_L03N_3 AG30 IO_L03P_3 AG29 ...

Page 178

... IO_L12N_4 V26 I/O 4 IO_L12P_4 U20 VCCO 4 IO_L13N_4 V20 VCCO 4 IO_L13P_4 W20 VCCO 4 IO_L14N_4 Y22 VCCO 4 IO_L14P_4 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number VCCO_3 V24 VCCO_3 AB24 VCCO_3 AD26 VCCO_3 V28 VCCO_3 AB28 VCCO_3 AF28 IO AA16 IO AG18 ...

Page 179

... DUAL 5 IO_L07N_5 AH16 DUAL 5 IO_L07P_5 5 IO_L08N_5 AJ16 GCLK 5 IO_L08P_5 5 IO_L09N_5 AK16 GCLK 5 IO_L09P_5 AH25 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L33P_4 AJ25 IO_L34N_4 AE25 IO_L34P_4 AE24 IO_L35N_4 AG24 IO_L35P_4 AH24 IO_L38N_4 AJ24 IO_L38P_4 AK24 VCCO_4 ...

Page 180

... VREF 6 IO_L03P_6 6 IO_L04N_6 AE13 I/O 6 IO_L04P_6 AJ14 DUAL 6 IO_L05N_6 6 IO_L05P_6 AH14 DUAL 6 IO_L06N_6 6 IO_L06P_6 AC15 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L29P_5/ AB15 VREF_5 IO_L30N_5 AD15 IO_L30P_5 AD14 IO_L31N_5/ AG15 D4 IO_L31P_5/ AF15 D5 IO_L32N_5/ AJ15 GCLK3 ...

Page 181

... I/O VRP_7 W3 I/O 7 IO_L01P_7/ W2 I/O VRN_7 W1 I/O 7 IO_L02N_7 W10 I/O 7 IO_L02P_7 V10 I/O 7 IO_L03N_7/ VREF_7 V9 I/O 7 IO_L03P_7 V8 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L31N_6 W5 IO_L31P_6 V6 IO_L32N_6 V5 IO_L32P_6 V4 IO_L33N_6 V2 IO_L33P_6 V1 IO_L34N_6/ U10 VREF_6 IO_L34P_6 U9 IO_L35N_6 U7 IO_L35P_6 U6 ...

Page 182

... I/O 7 VCCO_7 L1 I/O 7 VCCO_7 L2 I/O 7 VCCO_7 M6 I/O 7 VCCO_7 M7 I/O 7 VCCO_7 M3 I/O N/A GND M4 I/O N/A GND www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L27N_7 M1 IO_L27P_7/ M2 VREF_7 IO_L28N_7 N10 IO_L28P_7 M10 IO_L29N_7 N8 IO_L29P_7 N9 IO_L31N_7 N1 IO_L31P_7 N2 IO_L32N_7 P9 IO_L32P_7 P10 ...

Page 183

... N/A GND P14 GND N/A GND R14 GND N/A GND T14 GND N/A GND U14 GND N/A GND www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number GND V14 GND AC14 GND AF14 GND AK14 GND M15 GND N15 ...

Page 184

... VCCAUX VCCAUX CCLK D17 VCCAUX VCCAUX DONE AG17 VCCAUX VCCAUX HSWAP_EN D21 VCCAUX VCCAUX M0 AG21 VCCAUX VCCAUX M1 D25 VCCAUX VCCAUX M2 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number VCCAUX AG25 VCCAUX F27 VCCAUX K27 VCCAUX P27 VCCAUX U27 ...

Page 185

... Table 107: User I/Os Per Bank for XC3S2000 in FG900 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 Table 108: User I/Os Per Bank for XC3S4000 and XC3S5000 in FG900 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 DS099-4 (v2 ...

Page 186

... I/O: Unrestricted, 481 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: Unconnected pins for 68 XC3S2000 ( ) XC3S4000, XC3S5000 (633 max user I/O) I/O: Unrestricted, 549 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: No unconnected pins ...

Page 187

R Bank I/O I/O I/O I/O L39N_1 I/O GND GND L26N_1 L21N_1 L15N_1 L11N_1 I/O I/O I/O I/O I/O I/O I/O L39P_1 L32N_1 L17N_1 L28N_1 L26P_1 L21P_1 L15P_1 L11P_1 VREF_1 GCLK5 I/O ...

Page 188

... XC3S5000. If the table entry is shaded tan, which only occurs on ball L29 in I/O Bank 2, then the unconnected pin on the XC3S4000 maps to a VREF-type pin on the XC3S5000. If the other VREF_2 pins all connect to a volt- age reference to support a special I/O standard, then also connect the N ...

Page 189

... VREF B17 GCLK N. A17 GCLK I www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L35N_0 E8 IO_L35P_0 D8 IO_L36N_0 B8 IO_L36P_0 A8 IO_L37N_0 D10 IO_L37P_0 C10 IO_L38N_0 B10 IO_L38P_0 A10 IO_L39N_0 G11 IO_L39P_0 F11 IO_L40N_0 B11 IO_L40P_0 A11 VCCO_0 B13 VCCO_0 ...

Page 190

... I B24 I J23 I K23 I F23 VREF www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L17P_1 G23 IO_L18N_1 D23 IO_L18P_1 E23 IO_L19N_1 A23 IO_L19P_1 B23 IO_L20N_1 K22 IO_L20P_1 L22 IO_L21N_1 G22 IO_L21P_1 ...

Page 191

... IO_L26P_2 G30 I/O 2 IO_L27N_2 H29 I/O 2 IO_L27P_2 H30 I/O 2 IO_L28N_2 H33 I/O 2 IO_L28P_2 H34 I/O www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L08N_2 J28 IO_L08P_2 J29 IO_L09N_2/ H31 VREF_2 IO_L09P_2 J31 IO_L10N_2 J32 IO_L10P_2 J33 IO_L11N_2 J27 IO_L11P_2 ...

Page 192

... IO_L09P_3/ P26 I/O VREF_3 P27 I/O 3 IO_L10N_3 P28 I/O 3 IO_L10P_3 T24 I/O 3 IO_L11N_3 U24 I/O www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number VCCO_2 D32 VCCO_2 H28 VCCO_2 H32 VCCO_2 L27 VCCO_2 L31 VCCO_2 N23 VCCO_2 N29 VCCO_2 N33 ...

Page 193

... Y28 I/O 3 VCCO_3 Y32 I/O 3 VCCO_3 Y31 I/O 3 VCCO_3 Y34 I/O 3 VCCO_3 Y33 I/O 3 VCCO_3 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L33N_3 W25 IO_L33P_3 Y26 IO_L34N_3 W29 IO_L34P_3/ W28 VREF_3 IO_L35N_3 W33 IO_L35P_3 W32 IO_L37N_3 V28 IO_L37P_3 ...

Page 194

... I/O 4 IO_L25P_4 AL26 VREF 4 IO_L26N_4 4 IO_L26P_4/ AM26 I/O VREF_4 AF25 I/O 4 IO_L27N_4/ AG25 I/O DIN/D0 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L08N_4 AH25 IO_L08P_4 AJ25 IO_L09N_4 AL25 IO_L09P_4 AM25 IO_L10N_4 AN25 IO_L10P_4 AP25 IO_L11N_4 AD23 IO_L11P_4 AE23 ...

Page 195

... VCCO 5 IO_L06N_5 AG20 VCCO 5 IO_L06P_5 AG24 VCCO 5 IO_L07N_5 AH27 VCCO 5 IO_L07P_5 AJ22 VCCO 5 IO_L08N_5 AL19 VCCO 5 IO_L08P_5 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number VCCO_4 AL24 VCCO_4 AM27 VCCO_4 AM31 VCCO_4 AN22 IO AD11 IO AD12 IO AD14 IO AD15 IO AD16 IO AD17 ...

Page 196

... I/O 5 VCCO_5 AL15 I/O 5 VCCO_5 AP15 I/O 5 VCCO_5 AN15 I/O 5 VCCO_5 AJ16 VREF 5 VCCO_5 5 VCCO_5 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L27P_5 AH16 IO_L28N_5/ AN16 D6 IO_L28P_5/ AM16 D7 IO_L29N_5 AF17 IO_L29P_5/ AE17 VREF_5 IO_L30N_5 AH17 IO_L30P_5 AG17 IO_L31N_5/ ...

Page 197

... I/O 6 IO_L33P_6 AE7 VREF 6 IO_L34N_6/ VREF_6 AE6 I/O 6 IO_L34P_6 AE5 I/O 6 IO_L35N_6 AE4 I/O 6 IO_L35P_6 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L15P_6 AE3 IO_L16N_6 AE2 IO_L16P_6 AE1 IO_L17N_6 AD10 IO_L17P_6/ AD9 VREF_6 IO_L19N_6 AD2 IO_L19P_6 AD1 IO_L20N_6 ...

Page 198

... VCCO 7 IO_L16N_7 W4 VCCO 7 IO_L16P_7/ VREF_7 Y12 VCCO 7 IO_L17N_7 Y8 VCCO 7 IO_L17P_7 G1 I/O 7 IO_L19N_7/ G2 I/O VREF_7 U10 I/O 7 IO_L19P_7 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO U9 IO_L01N_7/ C1 VRP_7 IO_L01P_7/ C2 VRN_7 IO_L02N_7 D1 IO_L02P_7 D2 IO_L03N_7/ E2 VREF_7 IO_L03P_7 E3 IO_L04N_7 F3 IO_L04P_7 F4 IO_L05N_7 F1 IO_L05P_7 ...

Page 199

... VREF N/A GND N/A GND U5 I/O N/A GND U6 I/O N/A GND U3 I/O N/A GND U4 I/O N/A GND U1 VREF N/A GND www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L40P_7 U2 IO_L41N_7 G3 IO_L41P_7 G4 IO_L44N_7 L6 IO_L44P_7 L7 IO_L45N_7 M1 IO_L45P_7 M2 IO_L46N_7 N7 IO_L46P_7 N8 IO_L47N_7 P9 IO_L47P_7 ...

Page 200

... GND AK30 GND N/A GND AK34 GND N/A GND AK5 GND N/A GND AK9 GND N/A GND www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number GND AM11 GND AM24 GND AM3 GND AM32 GND AN1 GND AN2 GND AN33 ...

Related keywords