CDB5460A Cirrus Logic Inc, CDB5460A Datasheet
CDB5460A
Specifications of CDB5460A
Related parts for CDB5460A
CDB5460A Summary of contents
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Single Phase, Bi-directional Power/Energy IC Features Energy Data Linearity: ±0.1% of Reading over 1000:1 Dynamic Range. On-Chip Functions: (Real) Energy, I ∗ and V , Energy-to-Pulse RMS RMS Conversion Smart “Auto-boot” Mode from Serial EEPROM Enables Use without ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 VREFOUT REFERENCE OUTPUT VOLTAGE........................................................................ 7 5V DIGITAL CHARACTERISTICS............................................................................................ 7 3.3 V DIGITAL CHARACTERISTICS........................................................................................ 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 SWITCHING CHARACTERISTICS .......................................................................................... 9 2. OVERVIEW ............................................................................................................................. 12 ...
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AC Gain Calibration Sequence ........................................................... 31 3.8.7.4 DC Gain Calibration Sequence ......................................................... 31 3.8.8 Duration of Calibration Sequence ....................................................................... 31 3.9 Phase Compensation ...................................................................................................... 31 3.10 Time-Base Calibration Register ..................................................................................... 32 3.11 Power Offset Register ................................................................................................... 32 3.12 Input ...
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LIST OF FIGURES Figure 1. CS5460A Read and Write Timing Diagrams.................................................................. 10 Figure 2. CS5460A Auto-Boot Sequence Timing.......................................................................... 11 Figure 3. Data Flow. ...................................................................................................................... 13 Figure 4. Voltage Input Filter Characteristics ................................................................................ 14 Figure 5. Current Input Filter Characteristics ................................................................................ ...
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CHARACTERISTICS & SPECIFICATIONS ANALOG CHARACTERISTICS (T = -40 °C to +85 °C; VA ±10%; VREFIN = +2.5 V; VA- = AGND = 0 V; MCLK = 4.096 MHz ...
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ANALOG CHARACTERISTICS Parameter Dynamic Characteristics Phase Compensation Range (Voltage Channel, 60 Hz) High Rate Filter Output Word Rate Input Sample Rate Full Scale DC Calibration Range Channel-to-Channel Time-Shift Error (when PC[6:0] bits are set to “0000000”) High Pass Filter Pole ...
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VREFOUT REFERENCE OUTPUT VOLTAGE Parameter Reference Output Output Voltage VREFOUT Temperature Coefficient Load Regulation (Output Current 1 µA Source or Sink) Reference Input Input Voltage Range Input Capacitance Input CVF Current Notes: 12. The voltage at VREFOUT is measured across ...
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V DIGITAL CHARACTERISTICS (T = -40 °C to +85 °C; VA ±10%, VD+ = 3.3 V ±10%; VA-, DGND = 0 V) (See Notes 3, 4, and 13) A Parameter High-Level Input Voltage All Pins Except ...
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SWITCHING CHARACTERISTICS (T = -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels: A Logic 0 = 0.0 V, Logic 1 = VD+; CL ...
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Figure 1. CS5460A Read and Write Timing Diagrams 10 CS5460A DS487F4 ...
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DS487F4 CS5460A 11 ...
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OVERVIEW The CS5460A is a CMOS monolithic power mea- surement device with a real power/energy compu- tation engine. The CS5460A combines two programmable gain amplifiers, two ∆Σ modulators, two high rate filters, system calibration, and rms/power calculation functions to ...
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DELAY DELAY SINC 2 VOLTAGE REG REG Configuration Register * PC[6:0] Bits ∆Σ SINC 4 CURRENT Figure 3) will be enabled on the other channel; in order to preserve the relative phase relationship between the voltage-sense and current-sense in- ...
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Note that the 24-bit signed output words are expressed in two’s complement format. The 24-bit data words in the CS5460A output registers represent values between 0 and 1 (for unsigned output registers) or between -1 and +1 (for signed ...
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MHz clock at XIN, and instanta- neous A/D conversions for voltage, current, and power are performed at a 4000 Sps rate, whereas and energy calculations are per- RMS RMS formed at ...
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The first 8 SCLKs are used to clock in the command to de- termine which register read. The last 24 SCLKs are used to read the desired register. After reading ...
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This isola- tion is achieved using three transformers. One transformer is a general-purpose voltage trans- former, used to supply the on-board DC power to the CS5460A. A second transformer is a high-pre- cision, low-impedance ...
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VAC N L Low Phase-Shift Potential Transformer Transformer To Service Figure 7. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line) 18 Voltage 200 Ω Ω 200 Transformer 0.1µF 12 VAC + 200µF 12 VAC * R V+ M:1 ...
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VAC 120 VAC 120 VAC Earth Ground Service To Service Figure 8. Typical Connection Diagram (One-Phase 3-Wire) DS487F4 L 2 500 Ω 500 Ω 0.1 µF + ...
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VAC Service To Service Figure 9. Typical Connection Diagram (One-Phase 3-Wire - No Neutral Available 500 Ω 1 kΩ 0.1 µF + 235 nF 100 µ ...
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FUNCTIONAL DESCRIPTION 3.1 Pulse-Rate Output As an alternative to reading the real energy through the serial port, the EOUT and EDIR pins provide a simple interface with which signed ener- gy can be accumulated. Each EOUT pulse repre- sents ...
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EXAMPLE #2: The required number of pulses per unit energy present at EOUT is specified to be 500 pulses/kW-hr; given that line-voltage is 250 V (RMS) and the maximum line-current (RMS). In such a situation, the nominal ...
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EOUT ... EDIR Figure 11. Mechanical Counter Format on EOUT and EDIR sented by one pulse, the CS5460A will issue a “burst” of one or more pulses on EOUT (and also possibly on EDIR). The CS5460A will issue as ...
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EOUT or EDIR) changes state. When the CS5460A must is- sue another energy pulse, the other output chang- es state. The direction the motor will rotate is determined by the order of the ...
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When the metering system is installed, the calibrator would be used to control calibration and/or to program user-speci- fied commands and calibration values into the EE- PROM. The commands/data will determine the CS5460A’s exact operation, when ...
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Application Note AN225 For more information on Auto-boot mode, see the AN225, “USING THE CS5460A AUTO-BOOT MODE”. 3.4 Interrupt and Watchdog Timer 3.4.1 Interrupt The INT pin is used to indicate that an event has taken place in the ...
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Energy Register is read at least once in ev- ery 5 second span. 3.5 Oscillator Characteristics XIN and XOUT are the input and output, respec- tively inverting amplifier to provide oscillation and can be configured as ...
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The Calibration Registers Refer to Figure 3 and Figure 21. Voltage Channel DC Offset Register and Cur- rent Channel DC Offset Register - Store additive correction values that are ...
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Note that when the calibration command is sent to the CS5460A, the device must not be performing A/D conversions (in either of the two acquisitions modes). If the CS5460A is running A/D conver- sions/computations in the ‘continuous computation cycles’ acquisition ...
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Filter In M odulator ffse t* * Denotes readable/writable register pins of the voltage/current channels to their ground reference level. (See Figure 17.) Offset and gain calibration cannot be done at the same time. This will cause ...
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Before AC Gain Calibration (Vgain Register = 1) 250 mV 230 mV Sinewave INPUT 0 V SIGNAL -230 mV -250 mV ≈ 0.65054 230 1 V Register = / x / √2 RMS 250 After AC Gain Calibration (Vgain Register ...
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With the default setting, the phase delay on the voltage channel signal is ~0.995 µs (~0.0215 de- grees assuming power signal). With MCLK ...
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The voltage/current-channel surge-current limits of 100 mA. This applies to brief voltage/current spikes (<250 ms). The limit for DC input overload situations. To prevent permanent damage to the CS5460A, the designer must include adequate protection circuitry in ...
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Input Filtering Figure 6 shows how the analog inputs can be con- nected for a single-ended input configuration. Note here that the Vin- and Iin- input pins are held at a constant DC common-mode level, and the varia- tion ...
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Note also that in addition to the time-constants of the input R-C filters, the phase-shifting properties of the voltage/current sensors devices may also contribute to the overall time-constants of the volt- age/current input sensor networks. For example, current-sense transformers and ...
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The common-mode rejection performance of the CS5460A is sufficient within the frequency range over which the CS5460A performs A/D conver- sions. Addition of such common-mode caps can actually often degrade the common-mode rejec- tion performance of the entire voltage/current ...
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Protection Against High-voltage and/or High-current Surges In many power distribution systems very likely that the power lines will occasionally carry brief but large transient spikes ...
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... VA- and DGND pins of the device con- nected to the analog plane. Note: Refer to the CDB5460A Evaluation Board for suggested layout details, as well as Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service ...
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Commands (Write Only) All command words are 1 byte in length. Commands that write to a register must be followed by 3 bytes of register data. Commands that read from registers initiate the output of 3 bytes of register ...
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Power-Down The device has two power-down states to conserve power. If the chip is put in stand-by state, all circuitry except the analog/digital clock generators is turned off. In the sleep state, all circuitry except ...
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Register Read/Write W/R This command informs the state machine that a register access is required. On reads the addressed register is load- ed into the output buffer and clocked out by SCLK. On writes the data ...
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Serial Port Interface The CS5460A’s slave-mode serial interface con- sists of two control lines and two data lines, which have the following pin-names: CS, SCLK, SDI, SDO. Each control line is now described. CS Chip Select (input pin), is ...
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Once the RESET pin is de-asserted, ...
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REGISTER DESCRIPTIONS Current AC Offset Register (1 x 24) Channel Voltage AC Offset Register (1 x 24) Channel Power Offset Register (1 x 24) Pulse-Rat e Register (1 × 24) Timebase Cal. Register (1 x 24) Configuration Register (1 ...
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RS Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned the reset cycle. DL0 When EOD = 1, EDIR becomes a user defined ...
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Current Channel DC Offset Register and Voltage Channel DC Offset Register Address: 1 (Current Channel DC Offset Register) 3 (Voltage Channel DC Offset Register) MSB -( Default** = 0.000 ...
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Pulse-Rate Register Address: 6 MSB Default** = 32000.00Hz The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a ...
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Power Offset Register Address: 14 MSB -( Default** = 0.000 This offset value is added to each power value that is computed for each voltage/current sample pair before being ...
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Status Register to activate the INT pin when the status bit becomes active. IC Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command. Can be deactivated ...
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CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate, which is usually 4 kHz. EDIR Set whenever the EOUT bit asserted (see below) if the accumulated energy is negative. EOUT Indicates that ...
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PIN DESCRIPTIONS Crystal Out CPU Clock Output Positive Digital Supply Digital Ground Serial Clock Input Serial Data Output Chip Select Mode Select Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input Clock Generator Crystal Out 1,24 ...
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Voltage 11 Reference Output Voltage 12 Reference Input Differential 15,16 Current Inputs Power Supply Connections Positive 3 Digital Supply Digital Ground 4 Negative 13 Analog Supply Positive 14 Analog Supply Power Fail Monitor 17 RESET 19 Other No Connection 18 ...
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PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.311 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” ...
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ORDERING INFORMATION CS5460A-BS 24-pin SSOP CS5460A-BSZ 24-pin SSOP 9. REVISION HISTORY Revision Date F2 September 2004 F3 August 2005 F4 November 2007 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To ...