CDK5560 Cirrus Logic Inc, CDK5560 Datasheet
CDK5560
Specifications of CDK5560
CDK5560-1
Related parts for CDK5560
CDK5560 Summary of contents
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kSps, 24-bit, High-throughput ± Features & Description Differential Analog Input On-chip Buffers for High Input Impedance Conversion Time = 20 μS Settles in One Conversion Linearity Error = 0.0005% ...
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CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the specified operating conditions. • Typical characteristics and specifications are measured at nominal supply voltages and T • VLR = 0 V. All voltages with respect ...
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ANALOG CHARACTERISTICS V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.; BUFEN = V1+ unless otherwise stated. Connected per Parameter Analog Input Analog Input ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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MCLK RDY CS SCLK( SDO Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) DIGITAL CHARACTERISTICS TMIN to TMAX 3.3V, ± 2.5V, ±5% or 1.8V, ±5%; VLR ...
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GUARANTEED LOGIC LEVELS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: ...
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RECOMMENDED OPERATING CONDITIONS ) (VLR = 0V, see Note 15 Parameter Single Analog Supply DC Power Supplies: Dual Analog Supplies DC Power Supplies: Analog Reference Voltage 15. The logic supply can be any value VL – VLR = +1.71 to ...
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OVERVIEW The CS5560 is a 24-bit analog-to-digital converter capable of 50 kSps conversion rate. The device is ca- pable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital ...
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To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY falls. Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are emptied ...
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Clock The CS5560 can be operated from its internal oscillator or from an external master clock. The state of MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and be ...
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Analog Input The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input. Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in These diagrams also illustrate a differential ...
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Typical Connection Diagrams The following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 V and - 2 49 47pF +2.048 V 4.99k -2.048 V 4.99k +2.048 -2.048 V 49.9 ...
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The following figure depicts the CS5560 device powered from a single 5V analog supply. 49.9 2.048 V 47pF 4.548 V 2.5 V 4.99k +0.452 V +4.548 V 2.5 V +0.452 V 49.9 4.096 V 47pF 4.99k +5 V +4.096 Voltage ...
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AIN & VREF Sampling Structures The CS5560 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher input impedance and therefore reduce the amount of drive current required from an external source. This helps ...
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Figure 9 through Figure 16 illustrate the performance of the converter with various input signal magni- tudes. 5.55 kHz 32k Samples @ 50 kSps Frequency (Hz) Figure 9. Spectral Performance 5.55 kHz, -12 dB 32k Samples ...
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Figure 15 illustrates the device with a small signal 1/1,000,000 of full scale. The signal input for is about 8.2 microvolts peak to peak, or about 17 codes peak to peak. with a signal at about 2.6 microvolts peak to ...
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Figure 17 illustrates the noise floor of the converter from 0 kHz. While the plot does exhibit some 1/f noise at lower frequencies, the noise floor is entirely free of spurious frequency content due to digital activity ...
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Digital Filter Characteristics The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter attenuation is 1.040 kHz when sampling at 50 kSps. 0.0 -0.0414 dB -0.2 -0.4 -0.6 -0.8 ...
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Serial Port The serial port on the CS5560 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. 3.10.1 SSC Mode If the SMODE pin is high (SMODE = VL), the serial ...
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Power Supplies & Grounding The CS5560 can be configured to operate with its analog supply operating from 5V, or with its analog sup- plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or ...
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Using the CS5560 in Multiplexing Applications The CS5560 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to achieve high signal to noise. This means that once a conversion is started, the converter takes many sam- ples ...
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At the same time the converter is performing a conversion on a channel from one bank of multiplexers, the second multiplexer bank is used to select the channel for the next conversion. This configuration al- lows the buffer amplifier for ...
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PIN DESCRIPTIONS Chip Select Factory Test Serial Mode Select Differential Analog Input Differential Analog Input Negative Power 1 Positive Power 1 Buffer Enable Voltage Reference Input Voltage Reference Input Bipolar/Unipolar Select Sleep Mode Select CS – Chip Select, Pin ...
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BP/UP – Bipolar/Unipolar Select, Pin 11 The BP/UP pin determines the span and the output coding of the converter. When set high to select BP (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential ...
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SCLK – Serial Clock Input/Output, Pin 23 The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK determines the rate at which data is clocked out of the SDO pin. If the converter is ...
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PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.311 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1.“D” and ...
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ORDERING INFORMATION Model Linearity CS5560-ISZ 0.0005% 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5560-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision Date PP1 MAR 2008 PP2 MAY 2009 Contacting Cirrus Logic ...