CDK5581 Cirrus Logic Inc, CDK5581 Datasheet
CDK5581
Specifications of CDK5581
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CDK5581 Summary of contents
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200 kSps, 16-bit, High-throughput ± Features & Description Single-ended Analog Input On-chip Buffers for High Input Impedance Conversion Time = 5 µS Settles in One Conversion Linearity Error = 0.0008% Signal-to-Noise = 80 dB S/(N ...
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CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the specified operating conditions. • Typical characteristics and specifications are measured at nominal supply voltages and T • VLR = 0 V. All voltages measured with ...
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ANALOG CHARACTERISTICS V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL, unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Parameter Analog ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
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MCLK RDY CS SCLK( SDO Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) DIGITAL CHARACTERISTICS TMIN to TMAX 3.3V, ± 2.5V, ±5% or 1.8V, ±5%; VLR ...
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GUARANTEED LOGIC LEVELS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: ...
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RECOMMENDED OPERATING CONDITIONS ) (VLR = 0V, see Note 16 Parameter Single Analog Supply DC Power Supplies: Dual Analog Supplies DC Power Supplies: Analog Reference Voltage 16. The logic supply can be any value VL – VLR = +1.71 to ...
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OVERVIEW The CS5581 is a 16-bit analog-to-digital converter capable of 200 kSps conversion rate. The analog input accepts a single-ended input with a magnitude of ±VREF / 2 architecture. The filter is designed for fast settling and settles to ...
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Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are emptied from the serial port or if the conversion data is not read and CS is held low, RDY ...
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Voltage Reference The voltage reference for the CS5581 can range from 2.4 volt to 4.2 volts. A 4.096 volt reference is re- quired to achieve the specified signal-to-noise performance. tion of the voltage reference with either a single +5 ...
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Output Coding Format The reference voltage directly defines the input voltage range in both the unipolar and bipolar configura- tions. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above zero, and the final code ...
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Typical Connection Diagrams The following figure depicts the CS5581 powered from bipolar analog supplies, +2.5 V and - 2.5 V. +2.048 -2.048 V CS3003 +2.5 V +4.096 Voltage Reference (NOTE 1) -2.5 V Figure 6. CS5581 ...
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The following figure depicts the CS5581 part powered from a single 5V analog supply and configured for unipolar measurement +2.048 V CS3003 / CS3004 +5 V +4.096 Voltage Reference (NOTE 1) Figure 7. CS5581 Configured for Unipolar ...
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The following figure depicts the CS5581 part powered from a single 5V analog supply and configured for bipolar measurement, referenced to a common mode voltage of 2.5 V. CS3003 / CS3004 Common Mode Voltage (2.5 V Typ.) CS3003 / CS3004 ...
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AIN & VREF Sampling Structures The CS5581 uses on-chip buffers on the AIN and the VREF+ inputs. Buffers provide much higher input impedance and therefore reduce the amount of drive current required from an external source. This helps minimize ...
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Figures 11 through 16 illustrate the performance of the CS5581 when driven by a 5.55 kHz sine wave at various amplitudes. In each case, the captured data was windowed with a seven-term window function that exhibits 4 attenuation ...
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Figure 16 illustrates the noise floor of the converter from 0 100 kHz. While the plot does exhibit some 1/f noise at lower frequencies, the noise floor is entirely free of spurious frequency content due to digital activity ...
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Digital Filter Characteristics The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter attenuation is 0.26347 dB at 100 kHz when sampling at 200 kSps. 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 ...
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Serial Port The serial port on the CS5581 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. 3.10.1 SSC Mode If the SMODE pin is high (SMODE = VL), the serial ...
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Using the CS5581 in Multiplexing Applications The CS5581 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to achieve high signal to noise. This means that once a conversion is started, the converter takes many sam- ples ...
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At the same time the converter is performing a conversion on a channel from one bank of multiplexers, the second multiplexer bank is used to select the channel for the next conversion. This configuration al- lows the buffer amplifier for ...
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Synchronizing Multiple Converters Many measurement systems have multiple converters that need to operate synchronously. The convert- ers should all be driven from the same master clock. In this configuration, the converters will convert syn- chronously if the same CONV ...
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PIN DESCRIPTIONS Chip Select Factory Test Serial Mode Select Analog Input Analog Return Negative Power 1 Positive Power 1 Buffer Enable Voltage Reference Input Voltage Reference Input Bipolar/Unipolar Select Logic Interface Return 2 CS – Chip Select, Pin 1 ...
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BP/UP – Bipolar/Unipolar Select, Pin 11 The BP/UP pin determines the span and the output coding of the converter. When set high to select BP (bipolar), the input span of the converter is -2.048 volts to +2.048 volts (assuming the ...
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SCLK – Serial Clock Input/Output, Pin 23 The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK determines the rate at which data is clocked out of the SDO pin. If the converter is ...
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PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.311 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1.“D” and ...
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ORDERING INFORMATION Model Linearity CS5581-ISZ .0008% 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5581-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision Date PP1 MAR 2008 Contacting Cirrus Logic Support For all ...