PCF8562TT/2,518 NXP Semiconductors, PCF8562TT/2,518 Datasheet
PCF8562TT/2,518
Specifications of PCF8562TT/2,518
Related parts for PCF8562TT/2,518
PCF8562TT/2,518 Summary of contents
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PCF8562 Universal LCD driver for low multiplex rates Rev. 05 — 19 May 2010 1. General description The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number PCF8562TT/2 PCF8562TT/S400/2 4. Marking Table 2. Type number PCF8562TT/2 PCF8562TT/S400/2 PCF8562_5 Product data sheet Ordering information Package Name Description TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm TSSOP48 plastic thin shrink small outline package; 48 leads; ...
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... NXP Semiconductors 5. Block diagram 21 V LCD LCD BIAS GENERATOR CLK CLOCK SELECT 12 AND TIMING SYNC 15 OSC OSCILLATOR SCL INPUT 10 FILTERS SDA Fig 1. Block diagram of PCF8562 PCF8562_5 Product data sheet BP0 BP2 BP1 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROLLER PCF8562 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. PCF8562_5 Product data sheet S23 1 S24 2 3 S25 4 S26 S27 5 S28 6 S29 7 8 S30 9 S31 SDA 10 SCL 11 SYNC 12 13 CLK OSC SA0 LCD BP0 22 23 BP2 24 BP1 Top view. For mechanical details, see Pinning diagram for PCF8562 All information provided in this document is subject to legal disclaimers. Rev. 05 — ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol SDA SCL SYNC CLK V DD OSC SA0 LCD BP0 to BP3 S0 to S22, S23 to S31 7. Functional description The PCF8562 is a versatile peripheral device designed to interface any microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments ...
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... NXP Semiconductors Fig 3. The host microprocessor or microcontroller maintains the 2-line I channel with the PCF8562. The internal oscillator is enabled by connecting pin OSC to pin V are generated internally. The only other connections required to complete the system are to the power supplies (V 7.1 Power-on reset At power-on the PCF8562 resets to the following starting conditions: • ...
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... NXP Semiconductors 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of ...
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... NXP Semiconductors Using Equation ∨ 1 bias is 2 ∨ 1 with 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( These compare with It should be noted that V PCF8562_5 Product data sheet 3, the discrimination for an LCD drive mode of 1:3 multiplex with ...
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... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (S (1) V (2) V (3) V (4) V Fig 4. PCF8562_5 Product data sheet n V LCD BP0 ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of Figure 6. (1) V (2) V (3) V (4) V Fig 5. PCF8562_5 Product data sheet V LCD BP0 LCD V SS ...
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... NXP Semiconductors (1) V (2) V (3) V (4) V Fig 6. PCF8562_5 Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD LCD LCD LCD S n LCD LCD LCD LCD state − LCD − LCD −V LCD V LCD LCD LCD 0 V state 2 − ...
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... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies (see Figure (1) V (2) V (3) V (4) V Fig 7. PCF8562_5 Product data sheet 7). V LCD LCD BP0 LCD LCD LCD BP1 LCD V SS ...
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... NXP Semiconductors 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see Figure 8). BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 (1) V (2) V (3) V (4) V Fig 8. PCF8562_5 Product data sheet V LCD ...
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... NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V 7.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to V The LCD frame signal frequency is determined by the clock frequency (f A clock signal must always be supplied to the device ...
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... NXP Semiconductors 7.10 Display RAM The display RAM is a static 32 × 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... NXP Semiconductors 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of ...
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... NXP Semiconductors the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration ...
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... NXP Semiconductors 7.16 Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL Fig 13. System configuration 7.16.4 Acknowledge The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 7.16.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 2 7.16.7 I C-bus protocol 2 Two I C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562. The least significant bit of the slave address that a PCF8562 will respond to is defined by the level tied to its SA0 input ...
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... NXP Semiconductors An acknowledgement after each byte is asserted only by the PCF8562s that are addressed via address lines A0, A1 and A2. After the last display byte, the I asserts a STOP condition (P). Alternately a START may be asserted to restart an I access. 7.17 Command decoder The command decoder identifies command bytes that arrive on the I The commands available to the PCF8562 are defined in Table 7 ...
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... NXP Semiconductors Table 9. Bit [1] The possibility to disable the display allows implementation of blinking under external control. Table 10. Bit Table 11. Bit PCF8562_5 Product data sheet Mode-set command bits description Symbol Value Description see Table fixed value - - unused E display status 0 disabled (blank) 1 enabled B LCD bias configuration ...
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... NXP Semiconductors Table 12. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 13. Bit [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. ...
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... NXP Semiconductors Table 14. Number of devices Internal circuitry Fig 17. Device protection circuits PCF8562_5 Product data sheet SYNC contact resistance V DD SA0 CLK OSC SYNC A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S31 V SS All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter LCD DD(LCD tot ...
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... NXP Semiconductors 10. Static characteristics Table 16. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current DD(LCD) Logic V power-on reset supply voltage P(POR) V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...
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... NXP Semiconductors 11. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter Clock f internal clock frequency clk(int) f external clock frequency clk(ext) t HIGH-level clock time clk(H) t LOW-level clock time clk(L) Synchronization t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay PD(drv) 2 [3] ...
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... NXP Semiconductors BP0 to BP3, and S0 to S31 Fig 18. Driver timing waveforms SDA SCL SDA Fig 19. I PCF8562_5 Product data sheet 1/f CLK t CLKH CLK SYNC t PD(SYNC BUF LOW t HD;STA 2 C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 05 — 19 May 2010 ...
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... NXP Semiconductors 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14 ...
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... NXP Semiconductors Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 20. Acronym CMOS CDM HBM ITO LCD LSB MM MSB MSL PCB RAM RMS SCL SDA ...
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... Release date PCF8562_5 20100519 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Corrected marking code of S400 type PCF8562_4 ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or 18 ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 7 ...