SM72482E/NOPB National Semiconductor, SM72482E/NOPB Datasheet - Page 9

• Manufacturer Part Number: SM72482E/NOPB
• Description: IC DRIVER GATE DUAL 5A SOIC-8
• Manufacturer: National Semiconductor
• Series: SolarMagic™r

Specifications of SM72482E/NOPB

• Configuration: Low-Side
• Input Type: Inverting and Non-Inverting
• Delay Time: 25ns
• Current - Peak: 3A, 5A
• Number Of Configurations: 2
• Number Of Outputs: 2
• Voltage - Supply: 3.5 V ~ 14 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Other names: SM72482E/NOPBTR

The schematic above shows a conceptual diagram of the
SM72482 output and MOSFET load. Q1 and Q2 are the
switches within the gate driver. R
the external MOSFET, and C
itance of the MOSFET. The gate resistance Rg is usually very
small and losses in it can be neglected. The equivalent gate
capacitance is a difficult parameter to measure since it is the
combination of C
(gate to drain capacitance). Both of these MOSFET capaci-
tances are not constants and vary with the gate and drain
voltage. The better way of quantifying gate capacitance is the
total gate charge Q
required by C
V
Assuming negligible gate resistance, the total power dissi-
pated in the MOSFET driver due to gate charge is approxi-
mated by
Where
F
For example, consider the MOSFET MTD6N15 whose gate
charge specified as 30 nC for V
The power dissipation in the driver due to charging and dis-
charging of MOSFET gate capacitances at switching frequen-
cy of 300 kHz and V
If both channels of the SM72482 are operating at equal fre-
quency with equivalent loads, the total losses will be twice as
this value which is 0.216W.
In addition to the above gate charge power dissipation, - tran-
sient power is dissipated in the driver during output transi-
tions. When either output of the SM72482 changes state,
current will flow from V
through the output totem-pole N and P channel MOSFETs.
The final component of power dissipation in the driver is the
power associated with the quiescent bias current consumed
by the driver input stage and Under-voltage lockout sections.
SW
GATE
= switching frequency of the MOSFET.
.
P
DRIVER
GS
P
= 12V x 30 nC x 300 kHz = 0.108W.
GS
DRIVER
and C
G
GATE
(gate to source capacitance) and C
in coloumbs. Q
CC
= V
FIGURE 2.
GD
to V
of 12V is equal to
GATE
for a given gate drive voltage
EE
IN
is the equivalent gate capac-
for a very brief interval of time
GATE
x Q
G
is the gate resistance of
G
= 12V.
G
x F
combines the charge
SW
30142207
GD
9
Characterization of the SM72482 provides accurate esti-
mates of the transient and quiescent power dissipation com-
ponents. At 300 kHz switching frequency and 30 nC load used
in the example, the transient power will be 8 mW. The 1 mA
nominal quiescent current and 12V V
12 mW typical quiescent power.
Therefore the total power dissipation
We know that the junction temperature is given by
Or the rise in temperature is given by
For SOIC-8 package θ
conditions of natural convection. For MSOP8-EP θ
cally 60°C/W.
Therefore for SOIC T
CONTINUOUS CURRENT RATING OF SM72482
The SM72482 can deliver pulsed source/sink currents of 3A
and 5A to capacitive loads. In applications requiring continu-
ous load current (resistive or inductive loads), package power
dissipation, limits the SM72482 current capability far below
the 5A sink/3A source capability. Rated continuous current
can be estimated both when sourcing current to or sinking
current from the load. For example when sinking, the maxi-
mum sink current can be calculated as:
where R
output stage of SM72482.
Consider T
package under the condition of natural convection and no air
flow. If the ambient temperature (T
of the SM72482 output at T
I
pulsed currents.
Similarly, the maximum continuous source current can be
calculated as
where V
which varies over temperature and can be assumed to be
about 1.1V at T
eters as above, this equation yields I
SINK
(max) of 391mA which is much smaller than 5A peak
DIODE
DS
(on) is the on resistance of lower MOSFET in the
P
J
(max) of 125°C and θ
D
= 0.216 + 0.008 + 0.012 = 0.236W.
is the voltage drop across hybrid output stage
J
T
(max) of 125°C. Assuming the same param-
RISE
T
RISE
T
RISE
= 0.236 x 170 = 40.1°C
J
= T
JA
= P
is equal to
J
J
is estimated as 170°C/W for the
(max) is 2.5Ω, this equation yields
D
− T
x θ
A
JA
= P
JA
A
+ T
) is 60°C, and the R
of 170°C/W for an SO-8
D
SOURCE
GATE
A
x θ
JA
supply produce a
(max) of 347mA.
www.national.com
JA
is typi-
DS
(on)